Research and Design of S3C2410 peripheral storage system

Abstract: To meet the needs of Linux to transplant the S3C2410 microprocessor system, the S3C2410 peripheral storage system is designed. In this paper, the addressing principle of S3C2410 is studied, and the entire process of its addressing to SDRAM is analyzed in detail based on the timing diagram of the chip. The control registers and pins related to the storage system design are introduced, and the hardware circuit connection diagram with flash and SDRAM is given. Finally, the storage system is initialized under the startup code U-boot. Embedded developers can expand the storage systems of other arm core Chips Based on their development needs.

Key words: S3C2410; Addressing principle; SDRAM addressing mechanism; U-boot

0 Introduction

Samsung launched the ARM920T-based 16/32-bit Proteus microprocessor S3C2410, which provides low-cost, low-power, and high-performance small microcontroller solutions for handheld devices and general applications. To reduce the cost of the entire system, S3C2410 provides a wide range of internal devices. The enhanced ARM architecture MMU is used to support wince, epoc32, and Linux. With the advancement and development of technology, the functions of electronic products are increasingly powerful, while embedded operating systems can effectively manage various functions and shorten the product development cycle, therefore, joint development of the microprocessor and the embedded operating system has become a trend. However, the on-chip storage resources of the microprocessor are limited. to port the embedded system, the storage system must be extended. For embedded system developers, an in-depth understanding of its storage system principles and effective management of the storage system are of great significance for the correct and efficient design of embedded system hardware and underlying software programming [1].

1 addressing principle of S3C2410

The ARM920T Kernel provides a 32-bit address bus that can access 4G (232) linear address space, while the internal address bus of S3C2410 is 30bit (haddr [29:0]), the maximum external address space that can be accessed is 230, that is, 1 GB of address space 0x00000000 ~ 0x3ffffffff, it can be seen that the S3C2410 only uses the 32-bit address bus of ARM920T, which is a one-to-one connection [1]. Table 1 shows that S3C2410 divides 1 GB of external address space into eight memory groups, each of which is 128 MB in size, 6 of which are used for Rom, SRAM, and other memory, two memory types are used for Rom, SRAM, and SDRAM. Based on the consideration of the chip size and cost, when the S3C2410 is externally addressable, Partial decoding is adopted, that is, the low-level address line is used for in-chip addressing of Peripheral memory, the high address line is used for the external addressing of the Peripheral memory. As shown in table 1, because the starting address and space of each memory group are fixed, for any external address to be accessed by the system, the high 3-bit haddr [29:27] of the internal address bus can be easily used to select which memory group (bank) the address belongs to, so as to activate the corresponding bank selection signal, the external address bus A [] is used to implement the internal addressing of the corresponding bank. The addressing range is 128 M (227 ), therefore, the access space of the peripheral address is 1 GB (MB × 8 ). This mechanism is used to complete the entire addressing process of the external address space.

Table 1 activation and address space allocation of memory group segments in S3C2410

Haddr29	Haddr28	Haddr27	Chip selection Signal	Chip Selection Control Register	Address Space
0	0	0	Ngcs0	Bankcon0	0x00000000 ~ 0x07ffffff
0	0	1	Ngcs1	Bankcon1	0x08000000 ~ 0x0fffffff
0	1	0	Ngcs2	Bankcon2	0x0000000 ~ 0x17ffffff
0	1	1	Ngcs3	Bankcon3	0x18000000 ~ 0x1fffffff
1	0	0	Ngcs4	Bankcon4	0x20000000 ~ 0x27ffffff
1	0	1	Ngcs5	Bankcon5	0x28000000 ~ 0x2fffffff
1	1	0	Ngcs6	Bankcon6	0x30000000 ~ 0x37ffffff
1	1	1	Ngcs7	Bankcon7	0x38000000 ~ 0x3fffffff

It is difficult to understand the process of access to the SDRAM address space by S3C2410, which is mainly related to the storage structure of the SDRAM. In order to better understand its addressing mechanism, the author takes the SDRAM chip hy57v561620b (32 MB) as an example to describe in detail. The internal storage structure of the chip is 4banks × 4m× 16bit, that is, there are 4 banks, each of which has 4 M half characters (16bit ). The Bank address can be determined through the connection between the BA [1:0] And the address bus's high position. The specific Ba [1:0] is connected to which address bit. Different SDRAM storage systems have different solutions, for more information, see [3]. The storage unit in each bank is uniquely identified by the row address and column Address [1], the chip uses the row address lock pin NRAs and column address lock pin NCAs to connect to the S3C2410 pin nsras (select the communication number for the SDRAM row address) and nscas (select the communication number for the SDRAM column address) respectively, obtain the line address and column address from the address bus. In addition, the number of bits of the column addresses can be in scan -- bankconn of bankconn (n = 6, 7 ).
[0-1]. 00 = 8-bit, 01 = 9-bit, 10 = 10-bit. The reset value is 00, that is, 8 bit.

In actual work, as shown in figure 1, in the 3rd bus clock, the SCS are low, indicating that the SDRAM is selected and the Bank address of the address line is sent together with the corresponding row address, this command is called "Row active" or "Row active ). In this case, SDRAM locks the row address (nsras is valid), but has not executed the write command (NWE is high level), because there is no column address (nscas is high level), the storage unit cannot be determined. After trcd (RAS to CAS delay), the SDRAM is selected again (SCS are low). At this time, the nscas is low, indicating that the online address of the SDRAM is a column address, at the same time, NWE is valid and write operations are executed. It can be seen that the send column address addressing command and the specific operation command (read or write) are also issued at the same time, so the "read/write command" is generally used to indicate column addressing, when the column address is selected, data transmission is triggered. So far, the addressing of SDRAM is complete. It can be seen that the address on the address bus is divided into line addresses and column addresses and transmitted separately to the SDRAM. Based on the above addressing mechanism, the address space of 32 m or larger can be addressable by the BA [1:0] and 12 address lines.

2 Introduction to memory controllers and related pins

2.1 register Introduction

S3C2410 memory controllers mainly include bus bandwidth and wait control registers (bwscon); bus control registers (bankconn: nGCS0-nGCS5); bank control registers (bankconn: nGCS6-nGCS7 ); refresh, banksize, and mrsr. For more information, see [3].

2.2 related pins

S3C2410 provides related pins to control memory access:

Group selection signal: nGCS0-nGCS5, ngcs6 (nscs0), ngcs7 (nscs1) PIN is used to select the corresponding memory group.

Access control signal: In order to implement three methods of arm memory access command LDR/STR byte, half word and word access, in the memory group of S3C2410, all address spaces except bank0 can be set to 8-bit, 16-bit, or 32-bit by programming. bank0 can be set to 16-bit or 32-bit. Pin nwbe [] (write byte enabling) to implement three access methods for the 8-bit Rom chipset, or if the SRAM does not use UB/lb (set in bwscon, connect to UB/lb. Pin NBE [] (byte allowable signal when using SRAM) is connected to UB/LB when using SRAM (whether it is set in bwscon. Dqm [] (SDRAM data shielding signal) pins enable access to three types of SDRAM. There are also nwait, nxbreq/nxback pins.

3. hardware circuit design

In the embedded system development experiment, the expanded Storage System of S3C2410 adopts 16 m E28F128J3A-150 nor flash chip of Intel, and 32 m hy57v561620b SDRAM chip of Hynix. The address space is allocated as follows: Flash is 0x00000000 ~ in bank0 ~ 0x07ffffff, while SDRAM is 0x30000000 ~ 0x37ffffff address segment, the specific circuit connection 2.

 

 

 

Figure 2 circuit connection between S3C2410 and flash and SDRAM

 

4. storage system initialization

U-boot is the German denx Group developed for a variety of embedded CPU open source bootloader program, the latest version is 1.1.6, this experiment uses U-Boot-1.1.4. U-boot is developed based on ppcboot and armboot. It is very mature and stable and has been used in many embedded system development processes. It supports a variety of target operating systems, of which the most comprehensive support for Linux is the best choice for Embedded Linux bootloader.

Because the Linux development board to be transplanted in this experiment is based on the S3C2410 Development Board, the smdk2410 Development Board has been successfully transplanted in U-boot, therefore, the u- boot template running on the smdk2410 Development Board is used to design the U-boot suitable for this experiment. The storage system initialization changes are as follows:

(1) The Flash Driver uses board, CMI, and Flash. c. c needs to swap bytes when writing data, so it deletes its write_short () and write_buff () functions, using the Board/EP7312/flash. the write_word () and write_buff () functions in C, and the flash. in C, change flash_base0_prelim to cmd_flash_base. Change flash_block_size to 0x20000 (the block size in e28f128j3a flash is 128 K ).

(2) The dram_init () function in board/smdk2410/smdk2410.c defines the actual address and actual size of the SDRAM. In this experiment, the size of SDRAM is 32 MB, So modify phys_sdram_1_size in include/configs/smdk2410.h to 0x02000000.

(3) Replace the following code with the original content in the/* flash and Environment Organization */column of include/configs/smdk2410.h.

# Define phys_flash_1 0x00000000/* flash bank #1 */
# Define phys_flash_size 0x01000000/* 16 MB */
# Define pai_flash_protection
# Define pai_flash_base phys_flash_1
# Define pai_monitor_base phys_flash_1
# Define cmd_max_flash_banks 1/* max Number of memory banks */
# Define pai_max_flash_sect 128/* max number of sectors on one chip */

# Define pai_flash_erase_tout (2 * cfg_hz)/* timeout for flash erase */
# Define pai_flash_write_tout (2 * cfg_hz)/* timeout for flash write */
# Define pai_env_is_in_flash 1
# Define pai_env_addr (phys_flash_1 + 0x60000)
# Define performance_env_size 0x20000/* total size of environment sector */

According to the above analysis, the initial information of SDRAM and flash is in smdk2410.c and Flash respectively. the C file is defined, and the last is through lib_arm/board. c file display_dram_config () and display_flash_config () functions to display.

 

5 conclusion

 

Based on the actual experiment, this paper analyzes the principle of the S3C2410 storage system, completes the hardware circuit design and software initialization of its peripheral storage system, and finally successfully implements access to the S3C2410 storage system. Developers can design an efficient storage system based on the author's research and design ideas and the required storage capacity and type.

 

The author's innovation point: from the research of the addressing principle of the S3C2410 chip and the analysis of the time sequence diagram of the storage chip, the hardware design and software programming of its peripheral storage system are realized, demonstrate the mutual access mechanism between S3C2410 and the peripheral storage system, and strive to make the design idea clearer, which is conducive to debugging of the embedded system and thus improves its stability.

 

References:

 

[1] yuan fquan et al.. Principle and Design of Storage System Based on 101. Microcomputer Information. (2): 99-

 

[2] arm9tdmi datasheet.pdf

 

[3] S3C2410X datasheettings

 

[4] Tian ze. arm9-embedded development experiment and practice. Beijing: Beijing University of Aeronautics and Astronautics Press. 2006.10