Research on DSP-based robot visual servo system

1. Introduction

Robot visual servo system is an important research direction in the robot field. It originated in the early 1980s s and has made great progress with the development of computer technology, image processing technology, and control theory, some systems are in use. Visual servo is different from what we usually call machine vision. visual servo uses the principle of machine vision to automatically obtain and analyze images. From the directly obtained image processing feedback information, rapid image processing, giving feedback signals in the shortest time, constitutes a closed loop control of the robot's position, to achieve control of the robot. It is precisely because the system achieves certain control for the purpose, so the image processing process in the visual servo system must be fast and accurate. This paper focuses on the fast and accurate requirements of robot visual servo system. In order to meet the needs of project research, we discuss and study the image feedback robot visual servo technology based on DSP.

　　2. system working principle and hardware composition

Image-based visual servo directly calculates image errors, generates control signals, converts them to Robot Motion spaces, drives the manipulator, and completes servo tasks. This method is not sensitive to Calibration Errors and spatial model errors.

For robot visual servo systems, real-time performance has always been an important issue that is hard to solve. The low speed of image acquisition and the long time required for image processing bring significant time lag to the system. In addition, the introduction of visual information significantly increases the calculation workload of the system. The image processing speed is one of the major bottlenecks affecting the real-time performance of the visual servo system.

The difficulty in real-time image processing design is how to process a large amount of image data within a limited time. From the perspective of human vision, the real-time effect can be achieved only when the processing speed of the image processing system is more than 25 frames per second, that is to say, the real-time image processing system must complete the operation and processing of an L image within 40 ms to ensure the real-time image processing. To achieve this processing speed, we adopt the DSP-based image visual servo method. Its structure 1 is shown.

Figure 1 DSP-based image feedback robot visual servo Structure

　　2.1 wtc6201pa BOARD Introduction

In this article, wtc6201pa board of wenting company is selected. The hardware composition of the board is 2.

Figure 2 hardware composition of the wtc6201pa Board

The wtc6201pa board is one of the EVM boards. It uses the DSP chip of TI corporation, the TMS320C6201 chip. The maximum clock frequency of the TMS320C6201 chip is 200 MHz. Each clock cycle can execute up to 8 instructions to achieve the fixed-point operation capability of 16000mips. It has the following main features:

• The modified Harvard bus structure is adopted. The independent program bus, data bus, and DMA bus enable parallel access to and from data and DMA operations.
• Pipeline processing is adopted, so that two or more different operations can be executed in duplicate, improving the program execution speed.
• EMIF has a high-performance external memory extended interface, which can be directly connected to sbsram for Synchronous burst static memory and SDRAM for synchronous dynamic memory for large-capacity and high-speed storage. It also includes direct asynchronous memory interfaces, it can be connected to static memory SRAM and read-only memory EPROM for small-capacity data storage and program storage. 64 K program memory integrated in the chip can be configured as cashe to improve program execution efficiency.
• The 16-bit host port can communicate with other CPU storage areas and peripheral circuits. In addition, the multi-channel DMA controller can map data in the bucket without CPU involvement, thus reducing the CPU workload.

At the same time, the high-speed synchronous memory sbsram (K × 32bit) and SDRAM (4 m × 32bit), two-way A/D converter, large-capacity FPGA device and external I/O interface are configured on the board, the McBSP interface is also provided on the board, which is compatible with the 5 v ttl level to facilitate communication between users and external systems. The wt6201pa Board meets the PCI local bus revision 2.1 protocol. The host can access all DSP resources and the user can load programs through the host. The wtc6201pa Board provides WIN98 and NT driver software and DSP application software (APIs). With this hardware platform and underlying software library, you can easily develop software.

　　2.2 system hardware implementation

We chose hardware resources such as the TMS320C6201 chip, FPGA, sbsram, SDRAM, dual-port RAM, PCI bus, and JTAG interface on the wtc6201pa board as the visual image processing unit, it is a system consisting of a PC main control machine, an image acquisition card, a CCD camera, and a robot control system, as shown in figure 3.

Figure 3 system principle diagram

　　The system process is as follows:

The CCD camera outputs standard full-TV signals, including image signals, composite synchronous signals, line signals, field invisibility signals, slot pulses, and front and back balanced pulses. The system uses DH-PCI-H image acquisition card of Beijing daheng company to realize video signal preprocessing. The CCD camera inputs video data into the image acquisition card. The image acquisition card collects video data according to the set window position, size, and method, and the collected data is stored in the computer memory. Image Transmission is controlled by an image card. The image transmission speed can reach 40 MB/s without the need of CPU.

If the acquisition method of the image acquisition card is 25 frames per second, the acquisition time of one frame is 40 ms. Each frame of the image consists of two parity fields, with a field frequency of 50Hz, that is, the scanning time is 20 ms. The image size is 512x512 pixels, 8 bits are quantified, and 256 gray-scale. The data volume of a single frame is 512x512x8 bits = kb. The storage of image data is separated by rows, that is, the image data of odd and even fields is stored in cross mode to form a complete image function.

 

C6201 uses the bootmode [] to set the chip auto-lifting mode. The loading process uses the host (HPI) Boot Mode. The external host initializes the CPU storage space through the host port. After the host completes all initialization, it sets the dspint bit in the host port control register to 1 to end the boot process. The CPU exits from the reset status and starts to execute commands at address 0.

After the system is powered on, the host initializes the system through the HPI port, mainly completing the settings of various registers, including EMIF, interrupt, DMA and other related register initialization operations. The host writes 1 to the dspint bit of the HPI control register to trigger DSP operation, and the system enters the waiting state. The CCD camera collects images in real time and stores them in the host memory after being processed by the image acquisition card. The memory buffer of the PC is full in one frame, and an interrupt signal is sent to the DSP. After the DSP responds, the image data is transmitted from the host memory through the HPI port to the sdram on the wtc6201pa Board through the PCI bus. The image data within the DSP control wave gate is transmitted to the internal data storage in DMA mode. Because DSP is a command structure processing chip, it has the advantages of good programmability and can process a large number of complex commands (determined by the size of the program's RAM address space, however, compared with FPGA, FPGA is a programmable logic device with strong fine-grained parallel processing and multi-level pipeline processing capabilities, however, its limited internal logical resources make it unsuitable for complex logical operations. Therefore, FPGA is used as the co-processor to complete the underlying operations, and then the DSP completes high-level operations. The two operations can run in parallel using pipelines to complete high-speed image processing. Image Data Transmission from FPGA to DSP uses dual-port RAM. After processing an image, the DSP sends a message to the host. After the host responds, the image processing result is transmitted to the PC memory through the PCI bus, the PC then sends the location deviation data signal to the servo control system to complete the servo task.

　　3. Image KNN Matrix

For the image feedback control mechanism of the robot visual servo system, the image KNN matrix is critical. It describes the relationship between motion in the robot space and Motion in the image feature space:

Formula (2) and (4) are two representation forms of the image yashield matrix, and are the basis for Visual Tracking Based on Image feedback. It should be noted that, in order to obtain the unique image feature vector, the image feature space dimension should be greater than or equal to the pose space dimension (N kg/m ).

The methods used to calculate the image KNN matrix include online estimation, empirical method, and learning method. The Online Estimation Method uses dynamic estimation to obtain the image file matrix. The empirical method can obtain the image file matrix through calibration or prior model knowledge. The learning method mainly uses offline teaching and neural network to obtain the file matrix.

　　Conclusion

This paper analyzes the basic principle of the robot visual servo system, and designs a visual system based on the TMS320C6201 and FPGA co-processing structure of the programmable logic device. It realizes the real-time processing of image acquisition and Image Target. In the lab, we built an experimental platform using the designed Visual System. The experiment proves that the designed visual system meets the real-time requirements of the robot visual servo system.

The author's innovation point: for robot visual servo systems, the real-time problem has always been an important issue that is hard to solve. This paper innovatively uses the TMS320C6201 chip to implement image processing of robot visual servo, and uses FPGA co-processing to improve the image processing speed. Experiments show that the designed system meets the real-time requirements of robot visual servo, it has broad industrial application prospects.