Research on FPGA/CPLD state machine Stability

Abstract: The state machine frequently used in FPGA/CPLD design often has some stability problems. Some solutions are proposed in this paper. Experiments show that this method effectively improves the overall efficiency.

 

With the emergence and development of large-scale and ultra-large FPGA/CPLD devices, the application of EDA technology, which uses HDL (hardware description language) as a tool and FPGA/CPLD device as a carrier, is becoming more and more extensive. from small electronic systems to large-scale SOC (systemonachip) design, it is everywhere. in FPGA/CPLD design, the state machine is the most typical and widely used time series circuit module. How to design a stable and reliable state machine is a problem we must face.

1. Features and FAQs of the state machine

Standard state machines are divided into Moore state machines and mealy state machines. the output of the Moore state machine is only related to the current State value, and the state changes only when the clock edge arrives. the output of the mealy state machine is not only related to the current State value, but also to the current input value. This feature makes the control and output more flexible, but also increases the design complexity. the principle 1 is shown in.

 
As shown in figure 1, it is easy to understand the structure of a state machine. But why do we need to use a state machine instead of a general time series circuit? This is because it has some advantages that are unmatched by General time series circuits.

• The structure of the state machine described in VHDL is clear, easy to read, easy to understand, and easy to troubleshoot;
• Compared with other time series circuits, the state machine is more stable, and the running mode is similar to the CPU, which is easy to implement sequential control.

The description of the state machine in VHDL is a high-level modeling, and the results are often unexpected to the designer:

1. The transition status is displayed when two statuses are switched.
2. Invalid status during running.
3. When an ideal result is combined on one device and transplanted to another device, it cannot be consistent with the result.
4. The state machine can work stably, but occupies too many logical resources.

This situation is more likely to occur when FPGA Devices are integrated. we must carefully design the state machine and analyze the internal structure of the state machine. The output signal in the state machine is the decoding of the current State value. When the State value of the State Register is stable, the output is also stable. after the synthesizer is integrated, a state storage circuit with trigger as the core is generally generated, and its stability is determined by this. if the rising edge of the clock signal reaches the same time for each trigger, the status value will be converted between the specified Status values in strict accordance with the design requirements. however, this is only an ideal situation. The actual CPLD/FPGA Devices generally cannot meet this demanding timing requirement, especially when these triggers are far apart after wiring, there are often some differences in the latency when clock reaches each trigger. this difference will directly lead to the transition of the state machine during state transition. When this delay increases, the state machine may enter an invalid state. this is the failure mechanism of the Moore state machine. for the mealy state machine, this situation is more common because the output at any time is related to the input.

2 Comparison of state machine design solutions
2.1 use enumerated data types to define Status values
In the design, the state value of the state machine is defined as the enumerated data type. The synthesizer generally expresses it as a sequence of binary numbers, and then generates a status storage circuit with the trigger as the core, the usage of registers is reduced, and the overall efficiency and circuit speed will be improved to some extent.

Example 1 state machine (VHDL) with an enumerated state valueProgram.

Library IEEE;
Use IEEE. std_logic_1164 all;

Entity example is
Port (CLK: In std_logic;
Mach_input: In std_logic;
Mach_outputs: Out std_logic_vector (0 to 1 ));

End example;

Architecture behave of example is
Type States is (st0, ST1, st2, st3); -- defines states as Enumeration type
Signal current_state, next_state: States;

Begin

State_change: Process (CLK) -- state change process

Begin

Wait until CLK 'event and CLK = '1 ';
Current_state <= next_state;

End Process state_change;
Combination: Process (current_state, mach_input)
...... -- Decode the output status value and assign a new value to "next_state". Omitted

End behave;

 
Figure 2 waveform after merging enumeration-type state machines
Example 1 is a four-state full-coding state machine, as shown in figure 2. from the enlarged part, we can see that the transition status "11" appears during the conversion from "01" to "10 ". from the microscopic analysis of the intermediate signal "current_state" state conversion process, the Status Register's high flip and low flip time are inconsistent, when the high flip speed is fast, the transition status is "11". When the low-position flip speed is fast, the transition status is "00 ". if the state machine has more status values, the probability of transition is higher. in a non-fully-coded state machine, the circuit enters an illegal state due to the feedback of this transition state. If the circuit does not have the auto-start function at this time, the circuit will not return to the normal working status.

Because the output signal of the state machine is often used for important control, such as three-state enabling and register resetting, this result is not allowed. How can we eliminate such transition states? One method is to use the Gray code to represent the status value.

2.2 Use gray code to indicate the status value
The gray code feature is that there is only one difference between any adjacent two data. This feature enables the Gray code to represent the State value state machine, the transition state caused by delay can be largely eliminated. the improved procedure in Example 1 is shown in example 2.
Example 2 uses the Gray code to represent the state machine of the state value.
Library IEEE;

Use IEEE. std_logic_1164 all;

Entity example is
Port (CLK: In std_logic;
Mach_input: In std_logic;
Mach_outputs: Out std_logic_vector (0 to 1 ));

End example;

Architecture behave of example is
Constant st0: std_logic_vector (0 to 1): = "00 ";
Constant ST1: std_logic_vector (0 to 1): = "01 ";
Constant st2: std_logic_vector (0 to 1): = "11 ";
Constant st3: std_logic_vector (0 to 1): = "10 ";
Signal current_state, next_state: std_logic
Vector (0to1 );

Begin

......

Endbebave;
Using this method, when the register status jumps between adjacent States, there is only one change, which greatly reduces the probability of generating a transition state. however, when there are multiple conversion paths in a state to the next state, there is no guarantee that there is only one change in the status jump, which will not be able to take full advantage of the gray code.

2.3 define the status value encoding of the "onehot" Style
Although one of the goals of the VHDL language is to stay away from hardware, it has not been fully implemented so far. Therefore, the VHDL program is still very different when integrated with different devices. particularly for FPGA Devices, when Gray is used to represent the State value and describe a simple state machine, unstable results may occur. when writing programs for FPGA Devices, we can define the status value as a "onehot" status code and slightly modify the previous example. See example 3.

Example 3 state machine with "onehot" Encoding

Library IEEE;
Use IEEE std_logic_00004.all;

Entity example is
Port (CLK: In std_logic;
Mach_input: In std_logic;
Mach_outputs: Out std_logic_vector (0 to 1 ));

Endexample;

Architecture behave of example is

Constant st0. std_logic_vector (0 to 3): = "0001 ";
Constant ST1: std_logic_vector (0 to 3): = "0010 ";
Constant st2: std_logic_vector (0 to 3): = "0100 ";
Constant st3: std_logic_vector (0 to 3): = "1000 ";

Signal current_state, next_state: std_logic vector (0 to 3 );

Begin

......
The simulation result 3 after the flex10k series devices are integrated is shown.

 
Figure 3 waveform after state machine synthesis using "onehot" Encoding
As shown in 3, after the input signal is stable, the output signal of the state machine is also stable. It is a good choice to define the State Code of this style to design the FPGA-based state machine.
However, when the input signal changes, the circuit is unstable. at this time, we can no longer find a solution from the status value encoding method. looking back at the schematic diagram of the state machine, it is not difficult to find that the output value of the State Register must conform to the established retention time constraints. although the above state machine uses different encoding methods, it cannot completely eliminate this transition state. We will slightly improve the circuit structure, as shown in a better structure 4. this structure of the state machine can effectively suppress the emergence of the transition state. this is because the output register only requires that the status value be stable at the edge of the clock. after the above program is improved, the program 4.

......
Architecture behave of example1is
Type States is (st0, ST1, st2, st3); defines states as Enumeration type

Signal current_state, next_state: States;
Signal temp: std_logic_vector (0 to 1); defines a signal used to import the output register

Begin
State_change: Process (CLK) -- state change process

Begin

Wait until CLK 'eventandclk = '1 ';

Current_state <= next_state;

Mach_outputs <= temp;

End Process state_change;

......

 
 
Figure 5 improved waveform after state machine Synthesis
Obviously, the stability of the state machine of this structure is better than that of the general structure. However, it occupies more logical resources and the speed of the circuit may decrease. This should be considered comprehensively during design.
In addition, to prevent the circuit from entering the illegal state, it can be designed as a self-starting structure. It is effective to add a "when others" Statement to the state machine described in VHDL..

3. Tips for selecting state machines with different encoding methods and structures
3.1 select different encoding styles for different structural devices
The CPLD device based on the product item structure is suitable for the design of the Full-coding state machine. The gray code is used in the full-coding state machine to represent the State value. This is a good Optimization Method for devices with few logical resources.

The FPGA device based on the lookup table structure is suitable for designing a state machine encoded in the onehot mode. This structure state machine uses only one binary number to represent a state, which improves stability, however, you need to use more logical resources.

3.2 select the state machine structure based on the Logical resource size.
When the status transition sequence of the designed State Machine Appears multi-path, the gray code is used to indicate that the status value does not have any effect, because some adjacent States are not just one different. when logical resources permit, you can consider adding a level-1 output register after the state machine to ensure that the output does not produce glitch, so that the state machine outputs stable and reliable signals.

 

Deep feelings:

Sequential mode: Gray Code

Complex: Full encoding + Reg

FPGA: Unique popularity

CPLD: Full Encoding

 

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