Research on STM32 independent watchdog IWDG and window watchdog WWDG

Research on STM32 independent watchdog IWDG and window watchdog WWDG

Daniellee_ustb 2014-9-25

1. Watchdog introduction

The watchdog thing is simple, but I believe most programmers don't pay enough attention to it. It is necessary to use the watchdog to ensure that the system is running normally. When we design products, code and hardware design defects or external electromagnetic interference can cause the system to crash, if it is not properly reset, the system reliability will be greatly compromised. Watchdog is divided into two types of software watchdog and hardware watchdog, the principle is to use a separate timer to time, out-of-date will produce a reset signal, the main difference to see if there is a separate hardware structure, if there is a hardware watchdog, if it is a common timer implemented by the software watchdog. STM32F407 has two watchdog: independent watchdog IWDG and window watchdog WWDG, below to discuss their features and usage.

2. Features of IWDG and its use

The IWDG is an independent watchdog with a system-independent clock that is much more similar to an off-chip watchdog, using a separate on-chip resistor-capacitance clock circuit timing, recording time = (Clock frequency (40KHz)/divide number) *iwdg_setreload (t),t< 0xFFF. That is, the maximum set reset time for the record is (1/40k) *256*0xfff = 26.2 S. Since the clocks used by IWDG are not accurate, they should be given a certain amount of headroom when feeding the dog due to the drift to produce certain changes. In addition, this clock and the system clock is not related, all can not be synchronized with the system interrupt, once the timing of the time to generate a reset signal, the system is too late to store the current running state will be restarted, can be used in low-demand occasions.

3. Features of WWDG and its use

The WWDG has a separate 7-bit timer that uses the system clock to generate system interrupts. Its timing is (1/PCLK1) * 4096) * Divide factor (max 8) * (0x7f–0x3f) = 58ms. The condition of its reset is:

(1) When the value of the counter is reduced from 0x40 to 0x3f

(2) When the watchdog is refreshed when the value of the counter is greater than the upper window value

A reset signal can be produced by satisfying any one of the strips. In general, the set window upper limit value is 0x7f, the lower value defaults to 0x40, the counter down to 0x40 will produce interrupts, the next 910US will be 0x3f reset the system.

Think about it and you can find three questions.

First, we can find that even if the maximum value is set, WWDG maximum timing is only 58ms, we do not need to run a small section in the larger program to add a feeding dog program, want to make its timing 5S or 10S time reset system should be how to deal with it.

Through the experiment I found a method, that is, in the interrupt function to make an additional counter, if the counter does not reach the set value, then reload the Feed dog Timer initial value, while the setpoint added 1, when the counter reached the set value, do not load feed the dog timer value, The watchdog timer is then reduced from 0x40 to 0x3f to produce a system reset. Using this method, you can extend the timing time to the 58ms* additional counter setpoint, which is not a problem for a few 10 seconds.

Second, when the extra counter reached the setpoint, at this time the program did not reset the extra counter in time, software or hardware errors, the system will be reset, we need to store some of the running process variables, only less than 1ms of time (from 0x40 to 0x3f the longest is about 910us) how enough.

This first write Wwdg_feed (0x7F) re-add timer initial value, and then transform our storage function, add some wwdg_feed (0x7F) function, so that it does not reduce to 0x40, storage work is done, no longer feed the dog, Then no longer feeding the dog after another interruption will reset the system.

Third, if a reset occurs, how to distinguish between the power-on reset or the watchdog reset it.

When initializing the WWDG, there is a rcc_getflagstatus (Rcc_flag_wwdgrst) that can be used to determine if a watchdog reset occurs, and if the reset is caused by a re-power-on, the value of the system defaults, if the watchdog is reset, this value will change, This allows for state recovery for both of these different states.