Research on video image data acquisition methods

Research on video image data acquisition methods

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Source: China Power Grid Author: Wang baiyan, Wu Zhihong, mi hongju

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There are many video image acquisition methods, divided into two categories: automatic image acquisition and processor-based image acquisition. The former uses a dedicated image acquisition chip to automatically collect images, generate frame memory addresses, and refresh image data. In addition to setting the collection mode, the master processor does not participate in the collection process. This method is characterized by a good real-time performance when the acquisition does not occupy the CPU, and is suitable for the acquisition of active images. However, the circuit is complicated and the cost is high. The latter uses the general-purpose video A/D converter to achieve image acquisition, and the automatic acquisition of Images cannot be completed. The entire acquisition process is completed under the control of the CPU, and the CPU starts A/D conversion, read A/D conversion data and store the data in frame storage. It is characterized by the CPU time used for data collection, which requires a high processor speed, but the circuit is simple, the cost is low, and easy to implement, which can meet the needs of some image acquisition systems. A video image data acquisition method is proposed based on the TMS320C5402 chip.

1 device Overview

1.1 tlc5510 Introduction

Tlc5510 is an 8-bit high-impedance parallel Analog-to-analog converter (CMOs) manufactured by Texas Instrument (TI. It relies on + 5 V single power supply and provides a minimum sampling rate of 20 MS/s. Compared with the flash converter, tlc5510 adopts a semi-flash memory structure and CMOS process, thus greatly reducing the number of comparator in the device. The chip size can be reduced while maintaining high-speed conversion and low power. Because it contains an internal sampling and holding circuit, it greatly simplifies the design of the peripheral circuit without the need for external reference voltage and precision resistance, only the internal reference resistance and vdda are used to form the reference voltage divider to realize the full range conversion of 2 v.

The internal structure 1 of tlc5510 is shown in.

As shown in figure 1: tlc5510 mode/number converter contains clock generator, internal reference voltage divider, 1 set of high 4-bit sampling comparator, encoder, latches, 2 sets of low 4-bit sampling comparator, encoder and 1 low 4 bit latches and other components. The tlc5510 external clock signal CLK generates three internal clocks through its internal clock generator to drive three sets of sampling comparator. The reference voltage divider can be used to provide reference voltage for the three comparator groups. The 4-Bit High Output A/D signal is directly provided by the 4-bit high encoder, while the 4-bit low sampling data is provided by two 4-bit low encoder. When an internal voltage divider is used to generate a 2 V reference voltage, refts short-circuited to the reft end and refbs short-circuited to the refb end.

1.2 about D Trigger 74hc74

Edge trigger is a trigger that adds an input signal immediately before the CP trigger arrives. The input end is subject to a short interference time and has a low possibility of interference. 74HC74 trigger is an edge trigger with preset (SD), zeroed (RD) input, and top hop edge trigger. The menu is shown in Table 1:

Table 1 shows that the trigger jumps when the clock signal jumps along. In addition, SD and RD are effectively controlled during normal operation to set a high potential.

1.3 introduction to TMS320C5402

TMS320C5402 is a fixed point 16 B, and uses an improved Harvard structure (one group of program storage bus, three groups of data storage bus, and four groups of Address Bus ), CPU with dedicated hardware logic, in-chip memory, in-chip peripheral devices, and a highly specialized instruction set. The processor chip features high integration, simple structure, convenient expansion, high tolerance, strong processing capabilities, and low power consumption. It is mainly used in speech processing, image acquisition and processing, pattern recognition, industrial control, and many other fields, meeting the requirements for fast, accurate, real-time processing and control of signals. Moreover, it has increasingly demonstrated its great superiority.

1.4 74f245 Introduction

74F245 is an octal bidirectional buffer with three-state output and capable of bidirectional transmission.
End and
The end serves as the effective control end and the Direction Control End respectively. After special calculation, the three-state output B end can effectively prevent the output bus from being overloaded and protect the chip.
,
When low potential is connected, end A is the output end and end B is the input end;
Low potential,
When high potential is connected, end A is the input end and end B is the output end;
When high potential is connected, the B-end output is in the high-impedance state. This article uses the second method.

2 circuit principle

The video image data acquisition circuit 2 consists of two-way buffer, video A/D converter, DSP processor, and so on.

During system initialization, the clock frequency of C5402 can be set to 20 MHz. Use the CLKOUT output of C5402 as the clock input of the trigger 74HC74, and the output of the trigger 74HC74 as the sampling clock input of the/D converter;
The signal is decoded with the A15 address line to generate the control signal of the effective control end of the/D converter TLC5510 and the buffer 74F245; the direction control signal of the bidirectional buffer 74F245
Generated by the output signal XF of C5402.

The sequence of I/O read and write memory is shown in 3:

Video signal acquisition Uses A/D as an I/O port of c5402 and uses the portr command to read the digital signal after A/D conversion. The clkout output signal of c5402 is sent to 74hc74, and the output signal of the trigger is used as the sampling clock signal of tlc5510 of A/D converter.
The signal is decoded from the A15 address line to generate the effective control signal of the/D converter. The video image signal is collected through the 19 pins of the/D converter, and the output result enters c5402 through the two-way buffer 74f245.

3 software implementation

The software mainly includes DSP programming and PC programming. The main task of DSP is to initialize, manage resources on the board, and complete the image and video processing algorithms. The focus of PC programming is to manage DSP operations and write application-layer software.

C program:

Assembler:

4 knots

The DSP-based processing chip uses other related chips and peripheral circuits to collect image information, which can effectively collect video image information in real time, provides a front-end hardware platform for LED display video display, image transmission, communication, and image processing. It is easy to implement in terms of hardware and software and has good application value.