Roxy bus data acquisition card based on plx9030

Abstract: This paper introduces the specifications and features of the PXI bus, the features, functions and usage of the plx9030 chip, and provides the use of plx9030 interface chip, hardware and software implementation method of A/D data acquisition card based on PXI specification.
Key words: PXI bus; plx9030; A/D data collection

The PCI extension for instrumentation bus specification is a bus standard for measuring and controlling instruments launched by Ni (National instuments) in September 1997. It is a PCI computer local bus (IEEE1014-1987 standard) based on the module instrument structure, the goal is to provide a technically excellent module instrument standard based on the PCI bus, constitute a PC-based high-performance low-price module instrument system. Its core is the Compact PCI structure and Microsoft Window Software, coupled with the timing and trigger signals of the VXI bus, this allows users to apply the superior performance of all PCI, including mechanical, electrical, and software, and Microsoft Windows software, to testing, measurement, data collection, and industrial control, meet the needs of users at different levels for testing, measurement, data collection and industrial automation without sacrificing measurement indicators and increasing development costs.

1. Specifications and features of the PXI bus
Based on PCI electrical specification, curiosity PCI mechanical specification, and VXI plug-and-play specification, the PXI bus specification expands 13 local buses: trigger signal line, clock signal line, formed by simulating the signal line. PXI also defines the software framework, which is convenient for integrating all the relevant device-driven software for the module.

1.1 features
The PXI 3u module has two interface connectors. J1 transmits the signal required by the 32-bit local bus, J2 transmits the 64-bit PCI transmission signal, and implements the signal of the PXI electrical characteristics. The PXI mechanical Specification defines a standard chassis that includes power supply systems, cooling systems, and plug-in module slots. Based on the requirements of Compact PCI in terms of mechanical structure, the ANSI310-C, IEC-297 and ieee1101.1 Eurocard specifications with a long history of application in industrial environments are adopted, the dimension of the 3u and 6u modules are supported. The features are as follows:
· PXI bus adopts the same as Compact PCI, 2mm pitch, high density, shielded, needle-hole, high reliability and impedance matching, and complies with international standard IEC-1076 connectors;
· In addition to directly porting all the mechanical specifications in the Compact PCI specification to the PXI specification, PXI also adds some components not available in the Compact PCI specification, specifications for cooling, temperature, humidity, vibration and impact;
· The PXI and Compact PCI specifications support the "hot swapping" function required by the fault tolerance system;
· One of the important features of PXI is the interoperability with Compact PCI products.

1.2 features
· Compatible with PCI electrical specifications;
5 V and 3 V power supply mechanisms are supported;
· Supports 32-bit or 64-bit data transmission;
· Bus bandwidth (32-bit: 132 Mb/s; 64-bit: 264 Mb/s );
Support for PCI-PCI Bridge Expansion and plug-and-play;
To meet the needs of the measurement and control module, the PXI bus provides a system clock of 33 MHz through the J1 connector, the J2 Connector provides 10 MHz TTL reference clock signal, TTL trigger bus, and 13-pin local bus. In this way, signal lines for functions such as synchronization, trigger, and clock can be directly obtained from the PXI bus, without the need for a wide range of connections and cables.
While retaining all the advantages of the PCI bus local Bus to meet high-precision timing, synchronization and data communication requirements.

1.3 The characteristics of the PXI Software
Good software compatibility is the development advantage of the PXI system. Applying familiar application software and operating systems directly to the PXI system is a major feature of the software of the PXI module instrument system.
The software used for automatic testing and control consists of four main components: system management software, applications, instrument-driven software, and I/O interface software. PXI defines microsofttm windows nttm and microsofttm windows 95tm as their standard software framework, and requires that all the instrument modules must carry the software architecture according to visa) the standardized driver for Windows devices makes PXI a system-level specification, which ensures easy integration and use of the system and further reduces the development cost and cycle of end users.

1.4 PXI signal GROUP AND ELECTRICAL REQUIREMENTS
The PXI signal group includes a signal mapped directly from Compact PCI to P1/J1, a 64-bit signal copied on P2/J2, and a private signal for the P2. The private signals of the PXI interface include the trigger bus, parameter clock, and signals required for the local bus and star trigger.

1.5 local bus
The local bus of the Chrysanthemum chain is set between adjacent Peripheral modules. The local bus is a user-defined bus with multiple purposes (13 line width ). The application covers the transmission of analog signals between the two modules until the high-speed data transmission with no influence on the PXI bandwidth is achieved. For most slots, the functions of the local bus are user-defined, but there are also dedicated settings defined by the PXI specification.
For the sake of system configuration, the local bus chassis configuration should be determined by the chassis initialization (. INI) file. The INI file column contains information about each slot and its location in the system. The system configuration software uses this information to determine whether the system is correctly configured together.

1.6 parameter clock: PXI-CLK10
The PXI provides a public reference clock for the synchronization function of multiple modules in the measurement and control systems. The PXI-CLK10 independently provides a 10 MHz clock for each peripheral slot. The PXI-CLK10 operates multiple modules synchronously based on common baselines. Its Low-latency quality is ideal for the assessment trigger protocol. The star trigger slot defines the pins that provide the external clock.

1.7 trigger bus
The PXI trigger bus provides module synchronization and communication. The wire that triggers the bus can be used for triggering or clock transmission. The PXI trigger bus consists of the following eight signals: PXI-TRIG [].
● Clock Transmission
● PXI trigger Protocol
● PXI asynchronous triggering
● Synchronization trigger by using PXI
In addition to bus-based PXI trigger, the PXI bus provides an independent trigger signal (PXI-STAR) for each slot, which is oriented according to the star-based trigger slot. The star trigger slot is adjacent to the system slot. The 13 local bus signals on the left are used as the star trigger signals. This allows a single star trigger slot to control and monitor the trigger of two PCI bus segments.

2. Hardware Design
2.1 features of plx9030 chips
Because the signal P1/J1 Of The Roxy bus is mapped directly from the Compact PCI, the most convenient and reliable way to access the Roxy bus is to use the PCI interface chip, the PCI interface chip used in this design is plx9030. The chip complies with pciv2.2 specifications and is applicable to 32bit-33mhz target link for PCI burst transmission to 132 MB/sec, the 60 MB/sec local bus operation causes sudden transmission to 240 MB/sec, the PCI target advance read mode (readed ahead mode), and the PCI target delayed write mode (delayed write ), it also provides CompactPCI heat exchange, pciv2.2 power management, pciv2.2vpd support, and is compatible with PCI bus signals of 3.3v and 5 V. Its structure 1.

 

, Plx9030 provides three physical bus interfaces: PCI bus, local bus interface, and serial EEPROM interface. This design is a 64-channel scanned A/D acquisition card with a collection rate of 100 K. The slave mode (direct slave) of data transmission between the local bus of 9030 and the PCI bus can meet the requirements, at the same time, 9030 also has 5 PCI-to-local address spaces, 9 programmable gpios, 4 programmable chip selection signals, and interrupt generator capabilities.
9030 the configuration information of the internal registers is written in the EEPROM. When power-on, 9030 automatically loads the serial EEPROM configuration information and reads and writes the configuration registers through the PXI bus.

2.2 Design of A/D Acquisition Card Based on plx9030
The 64-Channel A/D converter card (A/D card for short) of the PXI bus can be inserted into any additional slot of the PXI 3u chassis. A/D card's PXI connector is connected to the chassis baseboard bus, and 68-wire sockets are connected to the input signal to the user end. A/D card consists of the interface control logic circuit, clock division circuit, 16-bit A/D conversion circuit and data input buffer circuit. It can convert the analog input signal into a 16-bit digital signal and send it to the computer. The structure of A/D card is shown in figure 2.

The external 16 MHz clock is initialized and set to 8254 to generate a sampling period control pulse of 0 to KB. Different gears can be selected through the program to control the sampling rate.
The A/D chip is designed with LTC1606, which has a resolution accuracy of 16 it and a maximum conversion frequency of 250 kHz. The chip comes with a sampling and holding amplifier and precision voltage reference. The voltage input is + 10 V ~ -10 V.
A 64-channel (single)/32-channel (differential) Acquisition channel is designed in the board. Under the control of the module-to-module conversion control logic circuit, the module-to-module conversion control logic sends a module-to-module conversion command (pulse) to ltc1601, and starts the module-to-module conversion on the corresponding hop edge, after the conversion is complete, the related circuit will automatically store the data collected during each sampling period in FIFO memory, which can be read through the PCI bus interface. This completes a sampling. For real-time, high-speed or burst data transmission, the interface circuit uses Asynchronous FIFO memory as the data buffer circuit.
In the design of the data collection and transmission system, the software query and interrupt technology are often used in two ways. The query method is relatively simple, but the processor needs to constantly read the status bit, A large amount of CPU time is used to increase the host time. In this case, the interrupt mode is used to write the interrupt signal to the interrupt register through 9030 linti, and read the data in the FIFO data memory through burst transmission.

 

3. Software Design:
The underlying driver of the PXI bus control template is implemented using WinDriver. WinDriver is a tool used to develop drivers. Using it to develop drivers is convenient and quick. Data collection and transmission are interrupted. When the OS is half full, an interruption signal is generated. In the interrupted service program, extract the data and place it in the Custom FIFO. The interrupt of the PCI Card is triggered by a level. If it is not cleared, the interruption will always exist and cause a crash. Therefore, an important task in the underlying interrupt program is to clear the interrupt mark. The clearing of the interrupt mark is to write a specific value to the interrupt register, which is related to hardware. Enable interrupt again in the interrupt service program:
The initialization of A/D card can be performed in the upper-layer control software. The PXI control panel is developed in the Visual C ++ environment. Data can be collected and displayed and stored in real time for any channel in 64 channels. You can set the collection frequency, collection time, gain, and input mode. Calibration can also be performed. After initialization, start a thread to retrieve the code value in the Custom FIFO, convert it to the corresponding voltage value, and store it in the file. In onpaint (), redraw the data curve. If you exit, the thread is aborted. The message and event triggering mechanism is used to make the program more flexible. Software initialization process 3.