From: http://student.csdn.net/space.php? Uid = 91306 & Do = Blog & id = 14644
The clock part is relatively easy. Now let's sort it out based on the datasheet idea.
I. basic understanding of clock the seventh part is "clock & Power Management". The summary is as follows: 1. The clock & Power Management Module of S3C2410 contains three parts: clock Control, USB control, and power control. The current focus is clock control. 2. There are two PLL (Phase Locked Loop, phase-locked loop, which has been learned in high frequency, which can achieve frequency doubling. The high frequency of S3C2410 is produced by this circuit ). One of them is mpll, M is the main, used to generate three kinds of clock signals: fclk (to provide the clock signal to the CPU core, we say the CPU clock speed of the S3C2410 is 200 MHz, this refers to the clock signal, corresponding, 1/fclk is the CPU clock cycle), hclk (for AHB Bus peripherals to provide the clock signal, AHB is advanced high-performance bus), pclk (for APB bus peripherals to provide the clock signal, APB for advanced peripherals Bus ). Here, you need to know about AMBA system architecture. You can download the relevant information from www.arm.com. In short, AMBA is a protocol that is known as the de facto standard for On-Chip fabric communication ). The AMBA protocol is an open standard, on-chip bus specification that details a stategy for the interconnection and Management of functional blocks that makes up a system-on-chip (SOC ). it facilitates "right-first-time" development of embedded processors with one or more CPU/signal processors and multiple peripherals. the AMBA protocol enhances a resuable design methodology by defining a CO Mmon backbone for SOC modules. we need to know that the AMBA bus is a solution proposed by arm. It is not the only specification, but because of the wide use of arm, the AMBA bus has become a de facto specification. Currently, the latest AMBA 3 specification version includes AMBA 3 Axi interface, AMBA 3 AHB interface, AMBA 3 APB interface, and AMBA 3 ATB interface. But S3C2410 only supports AMBA 2 specification. This version includes AMBA 2 AHB interface and AMBA 2 APB interface. That is, the two bus interfaces shown in the diagram of S3c2410.
Note that the peripherals connected to the two bus are different. AHB Bus connects high-speed peripherals, while low-speed peripherals are connected through APB bus. Obviously, different clock signals should be used for peripherals on different bus. AHB Bus corresponds to hclk and APB bus corresponds to pclk. So we should know in advance that the peripherals corresponding to each bus have those, so that after the clock signal is set, the initialization value of the corresponding peripherals will be determined accordingly.
The peripherals on the AHB Bus have LCD controller (cont stands for controller and controller) USB Host cont, extmaster, Nand cont, nand flash Boot Loader, bus cont, interrupt cont, power management, memory cont (SRAM/NOR/SDRAM, etc ).
Peripherals on APB bus include UART, USB device, SDI/MMC, Watch Dog Timer, bus cont, SPI, IIC, IIS, gpio, RTC, ADC, Timer/PWM.3. The main clock source is an external crystal oscillator or an external clock. After resetting, although mpll is enabled by default, if the value is not written to mpllcon, the external crystal oscillator is directly used as the system clock. EDUKIT-III has two external crystal oscillator, one is used for the system clock, 12 MHz; one is used for RTC, 32.768 kHz. The previous experiment did not write a value to mpllcon, so the system clock is 12 MHz. We can also find a problem here. If the external crystal oscillator is not soldered, the system cannot start normally. According to the above rules, no mpllcon is written after the reset, and there is no available clock source, so it will not start. That is, after the hardware is completed, the 12 MHz crystal oscillator must be soldered to perform subsequent hardware testing. 2. To set clock, first read the following section:
Power-On Reset (xtipll)
Figure 7-4 shows the clock behavior during the power-on Reset sequence. the crystal oscillator begins oscillation within several milliseconds. when nreset is released after the stabilization of OSC (xtipll) clock, the PLL starts to operate according to the default PLL configuration. however, PLL is commonly known to be unstable after power-on reset, so fin is fed directly to fclk instead of the mpll (PLL output) before the software newly configures the pllcon. even if the user does not want to change the default value of pllcon register after reset, the user shoshould write the same value into pllcon register by software.
The PLL restarts the lockup sequence toward the new frequency only after the software configures the PLL with a new frequency. fclk can be configured as PLL output (mpll) immediately after lock time.
|
This is mainly based on the characteristics of PLL. A simple description is that after power-on reset, the crystal oscillator starts to vibrate after several Ms. When the OSC clock signal is stable, the nreset level is increased (this is the process of Automatic hardware detection ). At this time, the PLL starts to work according to the default PLL configuration, but the particularity is that the PLL is unstable after the power-on reset, therefore, the S3C2410 is designed to use fin directly as fclk after power-on reset, which does not work for mpll. To enable mpll to work, write the mpllcon register value and wait for the locktime time before the new fclk starts to work. The following describes these steps, and the software Steps are combined with the program. 1. After several MS of power-on, the crystal oscillator output is stable. Fclk = crystal oscillator frequency. After the nreset is restored to a high level, the CPU starts to execute commands. This is completely a hardware action and does not require software settings. 2. Step 1: Set the p m s divider control, that is, set the mpllcon register. For more information about PMS, see Figure 7-2. Register mpllcon settings. In fact, there are certain rules, not every fclk frequency you want can be obtained. The official recommendation of a table PLL value selection table, follow this. Otherwise, you need to calculate by yourself according to the formula, but mizi does not guarantee that your settings are appropriate. Therefore, if you want to work at 200 MHz, follow the recommended value of Vivi.
@ Step1: Set p m s divider Control
MoV R1, # clk_ctl_base
LDR R2, = vmpllcon_200
STR R2, [R1, # ompllcon] |
Mdiv = 0x5c, pdiv = 0x04, sdiv = 0x00. formula mpll (fclk) = (m × fin)/(p × (2 ^ s) [M = mdiv + 8, P = pdiv + 2, S = sdiv 3. Step 2: Set clkdivn. This step sets the frequency division coefficient, that is, fclk is the CPU clock speed, hclk is obtained by fclk, and pclk is obtained by hclk. Assume that the hclk is the two-way division of the fclk and the pclk is the two-way division of the hclk, then the Division coefficient ratio is fclk: hclk: pclk =. Then the hclk is 100 MHz, and the bus clock cycle is 10ns. Pclk is 50 MHz.
@ Step2: Change clock divider
MoV R1, # clk_ctl_base
MoV R2, # vclkdivn
STR R2, [R1, # oclkdivn] |
4. Step 3: Add clkdivn Configuration
If hdivn = 1, the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus mode using following instructions.
Mmu_setasyncbusmode
MRC P15, 0, R0, C1, C0, 0
ORR r0, R0, # r1_nf: Or: r1_ia
MCR P15, 0, R0, C1, C0, 0
If hdivn = 1 and the CPU bus mode is the fast bus mode, the CPU will operate by the hclk. this feature can be used to change the CPU frequency as a half without affecting the hclk and pclk. |
After reading the previous paragraph, you only need to translate it.
@ Fclk: hclk =
. Macro mmu_setasyncbusmode
MRC P15, 0, R0, C1, C0, 0
ORR r0, R0, # (r1_ia | r1_nf)
MCR P15, 0, R0, C1, C0, 0
. Endm
@ Step3: Set asynchronous bus mode
Mmu_setasyncbusmode |
5. Step 4: Wait for the locktime to bring the new fclk into effect.
@ Step4: Stay locktime
MoV R1, # clk_ctl_base
LDR R2, = vlocktime
STR R2, [R1, # olocktime] |
6. The impact on peripherals in this experiment mainly involves two changes: one is uart and the other is SDRAM. (1) UART, which is connected to the APB bus, so the corresponding clock signal is pclk, which is now 50 MHz. If you want to set the baud rate to 115200bps, the value is calculated based on the formula ubrdiv0 = (INT) (pclk/(BPS * 16)-1, which is 26. If you put it in the program, you should pay attention to the form. The details are as follows:
Ubrdiv0 = (INT) (pclk/16./uart_baud_rate)-1 ); |
(2) The main influencing factor of SDRAM is the refresh frequency. No specific analysis is provided in the preceding section. You can describe it in detail now. With two pieces of HY57V561620CT-H, view the manual with a refresh frequency of 8192 refresh cycles/64 ms, so the refresh cycle is 64 ms/8192 = 7.8125us. Check the setting of each bit of the refresh register: · refen [23]: Enable automatic mode, set to 1 · trefmd [22]: Set to auto refresh mode, set it to 0 · TRP []: Check the RAS precharge time, check the SDRAM manual, and find that the-H series parameter is at least 20 NS. Now the clock cycle of the hclk is 10 ns, therefore, it should be at least 2 clock. It can be set to 00 · tsrc: Semi row cycle time, that is, Ras cycle time, which must be at least 65 ms. Therefore, at least 6.5 clock is required, it should be set to 11. Refresh []: formula refresh period = (2 ^ 11-refresh_count + 1)/hclk, then, refresh_count = 2 ^ 11 + 1-refresh period * hclk is exported. Bringing the value into the system and calculating it to 1268 = 0x04f4. This value should be rounded to reduce the error. · The remaining reserved values are set to 0, so that the value of this register should be 0x008c04f4. III. The conclusion is tested and runs stably on the Development Board. The source code is as follows:
