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1.MMU Introduction The MMU Management Unit, Memory Management Unit, primary responsibility: mapping virtual addresses to physical addresses, providing hardware-mechanism memory access checks. 2. Basic concept virtual address (Vsan Address,va), modified virtual address (Modified VA), Physical address (phisical addresses)VA is the address used by the CPU, MVA is used by MMU, caches, PA is memory device use, their mapping Relationship: (1) The CPU sees VA (2) caches and MMU using MVA, (3) The actual physical device used is PA. 3. The transformation of the basic concept address in address translation is like mapping in mathematics, using function formulas, many to 1,is that multiple virtual addresses correspond to the same physical address。Here the address conversion is the way of the page table：
A page table is a physical table of table items (Entry, also known as descriptors), each page table entry or a physical page (a piece of physical memory, a size of 1k,4k), or an address of a two-level page table (which can be called a page descriptor when it is the address of a Level two page table). All page tables are accessed with a physical address.
- Classification of table entries (descriptors)
The content that is saved by the descriptor can be divided into two categories. A class holds the starting address of a direct physical page or segment, such as a segment descriptor, a large page, a small page, and a minimal page descriptor. The other class holds the physical address of the two-level page table, such as the thick page table descriptor and the thin page table descriptor.
- First-level mapping and level two mapping
First-level mapping refers to the conversion of segments (section, size 1MB). A secondary mapping is a page-by-mode conversion. The ARM page size consists of three types: 1k,4k,64k. 4. The process of address translation
- VA->MVA:CPU emits a VA, how is it converted to MVA
This can be seen in the conversion through a hardware circuit. In ARM9, if va<32m, use the process identification number PID conversion to get the MVA process as follows: if (VA < 32M) MVA = VA | (pid<<25) Else MVA = VA Only the above process is implemented by hardware. This is a first-level mapping for VA, why?in the Linux system, the address space of each process is 0-4g,0-3g, called the user space, 3g-4g is the system, called the kernel space, all processes are shared。 If two processes are used in aVA has overlap, you need to rebuild the page table, invalidate caches, and tlbs in order to map the overlapping VA to different PA when switching processes. MVA is used to enable the process to use different MVA in the same case as the VA, and the PA is also different. This is the addition of a time between VA and PA toThe significance of the MVA mapping。
- Conversion of MVA->PA:MVA to PA
As stated above, there are two ways to convert a virtual address to a physical address: Formula map + page table conversion. The concept is also described above. The actual conversion instructions are described here.first, given a MVA, to convert, first to find a Level page table, how to find? There is a register,
TTB Register, the page table base address register, which is responsible for saving the base addresses of the primary page table, is of course the physical address. The TTB register is the TTB format integrated in the CP15 coprocessor: Therefore, the address of the first-level page table is 16k aligned because [14:0] requires 0. Descriptor format for a page table: A table entry for a first-level page table, which can be a segment descriptor, a thick page table descriptor, or a thin page table descriptor. The common denominator is that each description nonalphanumeric represents the physical address space of 1MB. Different points: The segment descriptor directly points to a 1MB address space and can be accessed directly, whereas a page table descriptor, as the name implies, points to a Level two page table, and another mapping is required. Two-level page Table Descriptor format: Two-level page table has two kinds: rough page table (Coarse page tables) + fine page table (Fine pages table) and thin page tables: The rough page table has a maximum of 256 table entries, each table entry can represent 4KB space, if the table entry is a large page table descriptor, Then 16 consecutive table entries represent the same large page descriptor. Each table entry in a fine-page table represents 1kb, points to a very small page, or expands to a small page of 4k and a large 64k page. This is the structure and format of the page table. Look below the specific process segment of the conversion address translation of a large page address translation small page address translation
S3C2440 's MMU
