S3C2440 clock description

The default operating frequency of the S3C2440 CPU is 12 MHz or 16.9344 MHz. The maximum operating frequency is 12 Mb. The use of the PLL circuit can generate a higher clock speed for the CPU and peripheral devices.
The S3C2440 has two PLL: mpll and upll, which are dedicated to upll and USB devices. Mpll is used for CPU and other peripheral devices.
Mpll generates three clock frequencies: fclk, hclk, and Plck. Fclk is used for CPU cores, hclk is used for AHB Bus devices (such as SDRAM), and pclk is used for APB bus devices (such as UART ).

 

 

1. After several milliseconds of power-on, the crystal oscillator output is stable. fclk = crystal oscillator frequency. After the nreset signal is restored to a high level, the CPU starts to execute commands.
2. We can start mpll at the beginning of the program. After setting several mpll registers, it takes some time (lock time) for mpll output to be stable. During this period of time (lock time), the fclk is stopped and the CPU is stopped. The length of lock time is set by the register locktime.
3. After the lock time, the mpll output is normal and the CPU is working under the new fclk.

 

 

 

 

 

Before proceeding, we will introduce the S3C2440 clock system. Generally, the main clock source of MCU is an external crystal oscillator.
Or external clock, and the most used is the external crystal oscillator. Under the correct circumstances, the clock used in the system is obtained after some processing by the external clock source. Because the frequency of the external clock source is generally unable to meet the needs of the system's high-frequency components, it is often necessary to perform frequency doubling of the PLL. In S3C2440, there are two non-PLL, one is mpll and the other is upll. Upll provides 48 MHz for USB. Here, we mainly introduce mpll. After mpll processing, the external clock source can obtain three different system clocks: fclk, hclk, and pclk. Fclk is the clock speed, used for ARM920T kernel; hclk is used for AHB Bus equipment, such as ARM920T, memory control, interrupt control, LCD control, DMA and USB main module; pclk is used for APB bus equipment, for example, the peripheral device's watchdog, IIS, I2C, PWM, MMC interface, ADC, UART, gpio, RTC, and SPI. These three system clocks (fclk, hclk, and pclk) have a proportional relationship, which is controlled by the hdivn bit and pdivn bit in the clkdivn register, therefore, as long as we know the fclk, and then through the control of the two, we can determine the hclk and pclk. How does fclk get it? It is obtained by inputting the frequency of the clock (that is, the external clock source) through a calculation formula (for specific formulas, see the Data Manual, this calculation formula also requires three parameters (mdiv, pdiv, and sdiv), which are obtained by configuring the register mpllcon. Finally, we use the clearest line to plot the Clock generation process: the external clock source → obtained through the mpllcon register
To fclk → use the clkdivn register to obtain hclk and pclk. The configuration process is completed in the startup file.

 

 

 

 

Uclk cannot be started normally under Low Frequency

 

Today, TPU took out a 2440 board for debugging, and found that despite various measures, USB host always does not work occasionally. the uclk is extracted through clkout0 and viewed with an oscilloscope. When it is found that it is not working, the uclk is not stable at all. so think carefully, there are several places that affect USB: 1. external oscillator 16.9344 MHz 2. the upll locktime of the locktime register 3. upllcon 4. the upll switches of the clkslow register are excluded one by one: 1. the crystal oscillator is used by mpll and upll. It has never been said that mpll is unstable. 2. it is suspected that the locktime is too large (0 xFFFF), but it cannot be changed. 3. it is useless to repeatedly set upllcon when the uclk is unstable. 4. when the uclk is unstable, switch the upll! When the uclk is stable and the upll is switched, the synchronization may fail. Why? Upll and mpll should be of the same structure, so mpll never has problems. upll only has a lower frequency than mpll. then we can look for it from the frequency. now we have set a relatively low frequency (such as 7 MHz) for upllcon. At this time, no matter how upll is switched, uclk is always unstable. now, sugon has appeared! Then a super high frequency (112 MHz) is set. Haha, it's not about how to switch upll, or power-on startup. uclk is very stable. the problem can be described as follows: upll cannot be reliably started at low frequencies. solution: first, give upll a high frequency, and then set the required frequency after it is stable. note: If you want to switch the upll switch in clkslow, follow this setting step. after this change, the TPU switching power supply is more than one hundred times, and the uclk is always very stable. this is only 2440, but it should also apply to 2410. you can test and verify it.