s3c2440 Shift Value u-boot-2016.03 4th support NAND Flash recognition

1,/include/configs/smdk2440.h
Added in
#define Config_cmd_nand
Compile
drivers/mtd/nand/built-in.o:in function ' nand_init_chip ':
/u-boot-2016.03/drivers/mtd/nand/nand.c:76:undefined reference to ' Board_nand_init '
Found that the files were missing
/DRIVERS/MTD/NAND/S3C2410_NAND.C Copy To
/DRIVERS/MTD/NAND/S3C2440_NAND.C Open the inside of all 2410 change for 2440

Drivers/mtd/nand/makefile
Add a row
obj-$ (config_nand_s3c2440) + = S3C2440_NAND.O

2, re-edit
Compilation passed, should not be used, burn write test machine
nand:0 MiB Although no error, but not real.

3, modify the code to support NAND FLASH
The 2410 and 2440 control registers are somewhat different, possibly for these reasons.
In Nand_scan () sweep NAND FLASH, do not come out of capacity size.
/drivers/mtd/nand/nand_base.c
ret = Nand_scan_ident (MTD, Maxchips, NULL);
if (!ret)
ret = Nand_scan_tail (MTD);
return ret;

Principle and NOR FLASH almost, do not come out ID comparison will know the size of

It's supposed to correspond to S3C2440_NAND.C inside.
int board_nand_init (struct nand_chip *nand)
{
Initialize the modifications, use the defined methods as much as possible, and facilitate later modification
CFG = s3c2440_nfconf_en; Cancel 15 bits not used in 2440 is reserved bit

Adding definitions in Smdk2440.h
#define Config_s3c24xx_custom_nand_timing
#define CONFIG_S3C24XX_TACLS 1
#define CONFIG_S3C24XX_TWRPH0 2
#define CONFIG_S3C24XX_TWRPH1 1
Remove Hardware ECC
#define CONFIG_SYS_S3C2440_NAND_HWECC

4, add #define DEBUG to open debugging information
Nand:board_nand_init ()
End of Nand_init
Hwcontrol (): 0xFF 0x83
Hwcontrol (): 0xFFFFFFFF 0x81
Dev_ready
Hwcontrol (): 0x90 0x83
Hwcontrol (): 0x00 0x85
Hwcontrol (): 0xFFFFFFFF 0x81
Dev_ready
Hwcontrol (): 0x90 0x83
Hwcontrol (): 0x00 0x85
Hwcontrol (): 0xFFFFFFFF 0x81
Dev_ready
Hwcontrol (): 0x90 0x83
Hwcontrol (): 0x40 0x85
Hwcontrol (): 0xFFFFFFFF 0x81
Dev_ready
Hwcontrol (): 0xFFFFFFFF 0x80
0 MiB

0x81 the last one is 1 indicates the selected
0x83. Selected
0x85. Selected
0x80 the last one is 0 is not selected

Board_nand_init () should also be problematic.
Plus enable Nfcont Controller
/* 4 ECC
* 1 CE first unchecked, when used in the selected
* 0 Start Flash Controller
*/
Writel (1<<4 | 1<<1 | 1, &nand_reg->nfcont);

Modify the check and command address register definition, note here is! Ncle
S3c24x0_hwcontrol ()
if (! ( CTRL & Nand_cle))
Io_addr_w |= s3c2440_addr_ncle;
if (! ( CTRL & Nand_ale))
Io_addr_w |= S3c2440_addr_nale;
Compare 2410 and 2440 to select a different control bit to make changes.
if (Ctrl & Nand_nce)
Writel (Readl (&nand->nfconf) & ~s3c2440_nfconf_nfce,
&NAND->NFCONF);
Else
Writel (Readl (&nand->nfconf) | S3C2440_NFCONF_NFCE,
&NAND->NFCONF);

Modify
#define S3C2440_NFCONF_NFCE (1<<1)
Other changes are also under the reference manual
#define S3C2440_NFCONF_EN (1<<15)
#define S3c2440_nfconf_512byte (1<<14)
#define S3C2440_NFCONF_4STEP (1<<13)
#define S3C2440_NFCONF_INITECC (1<<12)
#define S3C2440_NFCONF_NFCE (1<<1)
#define S3C2440_NFCONF_TACLS (x) ((x) <<12)
#define S3C2440_NFCONF_TWRPH0 (x) ((x) <<8)
#define S3C2440_NFCONF_TWRPH1 (x) ((x) <<4)
#define S3c2440_addr_nale 8
#define S3c2440_addr_ncle 0xc

Nane_base.c
Here's a look at the unchecked feature in the default Nand_base
static void Nand_select_chip (struct mtd_info *mtd, int chipnr)
{
struct Nand_chip *chip = mtd->priv;

Switch (CHIPNR) {
Case-1:
Chip->cmd_ctrl (MTD, nand_cmd_none, 0 | Nand_ctrl_change);
Break
Case 0:
Break

Default
BUG ();
}

The corresponding S3c2440_nand is called here.
Writel (Readl (&nand->nfcont) | S3C2440_NFCONF_NFCE, &nand->nfcont);

s3c2440 Shift Value u-boot-2016.03 4th support NAND Flash recognition