s3c2440 UART Serial Port driver

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This article is reproduced from the Mr_raptor column, thanks to Mr_raptor great God.

http://blog.csdn.net/mr_raptor/article/details/6556133

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The universal asynchronous receiver and transmitter (Universal asynchronous receiver and transmitter) are referred to as UART. Typically, the communication interface is configured by default in the embedded device. This is because many embedded devices do not have a display, can not get embedded device real-time data information, through the UART serial port and HyperTerminal connected to print embedded device output information. And in the tracking and debugging of embedded system,UART serial port is the necessary means of communication. For example: Network routers, switches, etc. are to be configured through the serial port. UART Serial port is also a lot of hardware data output of the main interface, such as the GPS receiver is through the UART serial port output GPS receive data.

The s3c2440 UART Controller provides three independent asynchronous serial I/O ports, each of which can operate in interrupt mode or DMA mode, in other words, the UART can generate interrupts or DMA requests for data transfer between the CPU and the UART. UART serial port hangs on the APB bus, the APB bus can reach up to 50MHz operating frequency, can achieve the highest 115.2Kbps baud rate communication speed when using the APB clock frequency. If the UART serial port receives external devices that provide UEXTCLK (external clocks), the UART can operate at a higher speed. Each UART serial port in the receiving device and the transmitter contains a 64Byte FIFO buffer, for the cache to send data and receive data.

Since the UART is a serial asynchronous communication mode, so in the UART communication process can only transfer 1bit, a number of bits constitute a data frame (frame), the frames are the most basic unit of the UART communication, it mainly includes: start bit, data bit, check bit (if the data check is turned on, to include the check bit), And stop bits, as shown in frame structure 1.

Figure 1 UART Data frame structure

The UART before communication in the sending side and the receiver to agree on a good frame structure, which is agreed to transfer data frame format.

Start bit: Must be included in the data frame to represent the beginning of a frame.

Data bits: Optional 5/6/7/8 bits, which can be specified by the programmer.

Check bit: If the data check is turned on, the bit must be specified.

Stop bit: Optional 1, 2 bits, this bit length can be specified by the programmer.

After the communication parties have agreed the frame format, specify the same baud rate to ensure the synchronization of data transmission between the two parties.

s3c2440 UART Serial Port working principle

Each UART contains a baud rate generator, transmitter, receiver and a control unit, shown in 2

Figure 2 UART Hardware structure

The UART is the asynchronous implementation of the communication, the sampling speed is determined by the baud rate, the baud rate generator can be operated by PCLK (peripheral frequency), fclk/n (frequency division of the CPU), UEXTCLK (external input clock) three clock as the input frequency, The baud rate setting register is programmable, and the user can set its baud rate to determine how often to send and receive. The transmitter and receiver contain 64Byte FIFO and data shifter. The UART communication is byte-stream oriented, and when the data is sent to the FIFO, it is copied to the data shifter (1 byte size), and the data is emitted by sending the data pin TXDN. Similarly, the receiving data receives data via the RXDN pin (1-byte size) to the receiving shifter, which is then copied into the FIFO receive buffer.

　　(1) Data transmission

The sent data frame is programmable, its frame length is user-specified, it includes a start bit, 5~8 data bits, an optional parity bit and one to two stop bits, the data frame format can be set by setting the Ulconn Register (3). The transmitter can also produce a termination signal, which consists of a data frame of all 0. After the current sending data is completely transferred, the module sends a termination signal. After the signaled signal is sent, it can continue to send data via FIFO or send hold Register (NON-FIFO).

　　(2) Data reception

The receiver data is also programmable, the receiver can detect overflow error parity errors, frame errors and termination conditions, each error can be set an error flag.

Overflow error refers to the old data being overwritten by the new data before the old data is read.

Parity error is when the receiver detects that the received data check result fails and the received data is invalid

Frame error refers to the received data does not have a valid stop bit, can not determine the end of the data frame

The termination condition refers to the transfer time that the RXDN receives to hold the logic 0 status longer than one data frame

　　(3) Automatic flow control AFC (Auto Float control)

　　UART0 and UART1 support automatic flow control with Nrts and Ncts, andUART2 does not support flow control. In the case of AFC, the nrts and ncts pins of both sides of the communication are connected to each other's ncts and nrts pins respectively . The software controls the sending and receiving of data frames.

When the AFC is opened, the sending side should determine the status of the NCTS signal before sending it, and send the data frame when the ncts activation signal is received. The ncts pins are connected to each other's nrts pins. The receiving end is ready to receive the data frame, its receiver FIFO has more than 32 bytes of free space, thenrts pin will send an activation signal, when it receives a FIFO less than 32 bytes of free space, Nrts must be deactivated. As shown in 3.

Figure 3 Automatic flow Control data transfer

　　(4) Baud rate

The baud rate generator in the UART provides a working clock for the transmitter and receiver. The baud rate generator's clock source can choose the s3c2440a internal system clock (PCLK,fclk/n) or uextclk (external clock source), which can set the input clock source of the baud rate generator by setting the UConn register. Usually we choose to use pclk as the UART working clock.

　　The UART controller does not have a register to set the baud rate, but instead sets a divisor factor to determine its baud rate. The formula is calculated as follows:

　　UART Divisor (ubrdivn) = (int) (UART clock/(Buadrate *))-1

which

　　The value range for UBRDIVN should be 1~2^16-1.

UART clock, can choose pclk,fclk/n or UEXTCLK

For example:

Baud rate of 115200bps,PCLK clock for its operating frequency, using 50MHz, then ubrdivn is:

　　UBRDIVN = (int) (50M/(115200 x 16))-1 = 26

When the system clock is uninitialized,PCLK = 12MHz, if the baud rate is 57600bps, then the ubrdivn is:

　　UBRDIVN = (int) (12M/(57600 x 16))-1 = 12

Of course, UBRDIVN should be from 1~ (2^16-1), which is set to 0 (bypass mode) only when using UEXTCLK less than PCLK.

　　(5) Error tolerance rate of baud rate (baud-rate error torlerance)

Data signal in the transmission process due to external electromagnetic interference, signal weakening and other reasons, when the clock frequency is low, high transmission rate will produce errors, when the error reaches a certain value, the data signal can not be recognized normally, resulting in communication anomalies. Good for example, in the ordinary train track to try to travel high-speed trains, as high-speed trains on the track requirements, when the speed reached a certain level, it is likely to cause accidents. The industry's baud rate has an error tolerance of 1.87% (3/160), and if it is larger than that, you should choose a lower baud rate or increase the input clock frequency.

The error tolerance rate is calculated as:

　　UART Error = (tupclk-tuexact)/tuexact * 100%

Note:

TUPCLK true working clock frequency for UART:TUPCLK = (ubrdivn + 1) * * * 1FRAME/PCLK

Tuexact for UART ideal operating clock frequency:tuexact = 1frame/baudrate

Where:1Frame is the length of the data frame = start bit + data bit + optional Check bit + stop bit

If the baud rate is 115200bps, thepclk clock is 50MHz, the baud rate divisor factor UBRDIVN is 26 (calculated by the previous UBRDIVN calculation formula), with 1 stop bits, 8 data bits, the error tolerance rate of the 8N1 mode of non-verified communication is:

TUPCLK = * + * 10/50m = 0.0000864

Tuexact = 10/115200 = 0.0000868

UART Error = | 0.0000864-0.0000868 | /0.0000868 = 0.46%

Before the development Board does not initialize the system clock, the Development Board works at 12MHz, if we set the baud rate to 115200bps, using PCLK as the system default clock 12MHz,8n1 data frame format communication, then:

　　UBRDIVN = (int) (12M/(115200 * 16))-1 = 6

Its error tolerance rate:

TUPCLK = 7 * * 10/12m = 0.0000933

Tuexact = 10/115200 = 0.0000868

UART Error = | 0.0000933-0.0000868 | /0.0000868 = 7.5%

The error tolerance rate is greater than 1.86%, so at 12MHz frequency, the baud rate cannot be set to 115200, now the baud rate is set to 56700bps, using 8N1 data frame format communication, then:

UBRDIVN = (int) (12M/(57600 * 16))-1 = 12

TUPCLK = * * 10/12m = 0.000173

Tuexact = 10/57600 = 0.0001736

UART Error = | 0.000173-0. 0001736 | /0. 0001736 = 0.345%

With the baud rate of 56700bps,8n1 data frame format communication, its error tolerance rate is less than 1.86% of the standard , so it can work properly.

MINI2440 UART Serial Port

Figure 4 MINI2440 Development Board serial hardware diagram

Figure4 formini2440 Development Board leads to uart serial connection diagram, which uses DB9 interface male, which has 9 signal lines, uart communication process used in the signal line 2 RSTXD0 (data send pin) it and the serial line of the female head TXDX Signal line (x represents No. 0, 2nd serial port), signal 3 RSRXD0 (data receiving pin) and serial line female rxdx-phase ( x for No. 0, 5 (grounding pin), signal line 7 RSCTS0 (data transmission flow control pin) and serial line female nctsx-phase, signal line 8 RSRTS0 (data receive flow control PIN) and serial line female nrtsx. If uart does not open afc flow control, as long as the signal line 2, signal line 3 and Signal line 5.

　　

Figure 5 MIMI2440 Serial pin wiring

As can be seen from Figure 5, TXD0 and RXD0 are connected to the GPH2 and GPH3 pins on the CPU, while GPH2 and GPH3 are CPU multiplexed pins, so we will set the GPH2 and GPH3 corresponding registers with the corresponding registers as shown in gphcon,6.

Figure 6 Gphcon Register

Cphcon[5:4] and Gphcon[7:6] set bits for the TXD and rxd pins, set their functions to the UART dedicated communication pin, so set to 0B10, respectively, for the transmission and reception of the UART data, i.e. Gphcon |= 0xa0

Figure 7 Gphup pull-up resistor setting register

Gphup pull-up resistor setting register: The pull-up resistor is used to stabilize the level signal, guaranteeing the correct transmission data, and setting its internal pull-up in the gphup, i.e. gphup=0x0

Figure 8 Ulconn Register

By setting ULCON0 to set UART0 communication mode, ULCON0[6] Select communication mode for normal mode operation or infrared TX/RX mode, Ulcon[5:3] set serial port 0 Check mode, ulcon0[2] set serial port 0 stop bit, ulcon0[1:0] Sets the number of data bits for serial port 0.

We choose ordinary communication mode, no check bit, 1 stop bit, 8 data communication mode, so: ulcon0=0x03;

Figure 9 UART0 Serial Controller register (UCON0)

Usually UART serial port adopts PCLK as input working clock, adopts simple polling method to receive and transmit data, does not turn on data receiving timeout, and produces error without error state interrupt, so ucon0=0x05

Figure ten UART FIFO control registers (UFCON0)

Figure One UART Modem control Register (UMCON0)

Figure one UART transmit/receive status register

Figure UART Send cache Register (UTXH0)

Figure UART Receive cache register (URXH0)

Figure UART Baud rate divisor Register (UBRDIV0)

The above register is the register associated with the UART communication, using a simple no FIFO, no automatic flow control AFC, set the following:

UFCON0 = 0x00; Do not use FIFO

UMCON0 = 0x00; Do not use flow control

UBRDIV0 = 26; Baud rate is 115200,pclk=50mhz

UBRDIV0 = 53; Baud rate is 57600,pclk=50mhz

UBRDIV0 = 12; Baud rate is 57600,pclk=12mhz

UTXH0 and URXH0 are data sending and receiving registers, sending data by polling method to determine the status of the sending State register, when the data can be sent, perform UTXH0 Register write operation, receive data, polling to detect the status of the receiving State Register, When data arrives, the serial data can be obtained by reading the data in the URXH0 register.

1 #defineTxd0ready (1<<2)//Send data status OK2 #defineRxd0ready (1)//Receive data status OK3  4 /*UART Serial Port single character printing function*/5 extern voidPUTC (unsignedCharc)6 {7      while( ! (UTRSTAT0 &txd0ready));8UTXH0 =C;9 }Ten   One /*UART Serial Port accepts a single character function*/ A externUnsignedCharGetcvoid) - { -      while( ! (UTRSTAT0 &rxd0ready)); the     returnURXH0; -}

s3c2440 UART Serial Port driver