S3c2440a Memory Design

S3c2440a Memory Design
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Author:Harlanstars (Harlan)
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2008/3/20 10:08:04 AM

In s3c2440a, memory storage is divided into eight banks, each of which is 128 M bit. The total size is 1G bit. bank0 ~ Bank5 is used in ROM/SRAM and bank6 ~ Bank7 is used in ROM/SRAM/SDRAM.
However, on the hard disk, only SDRAM 512 M bit (2ch 128 Mbit)/AMD rom 1 M bit * 16 bit/NAND Flash 64 M * 8 bit. how to map the SDRAM on the hardware to the bank 0 ~ Bank 7 ??
Zookeeper

Author:Harlanstars (Harlan)
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2008/3/20 02:25:29 pm

In this case, there is a memory space of 1 GB (bytes) in the internal part of s3c2440a. Should this be done?
Then it is divided into eight banks. The NAND Flash is not here, And the SDRAM is in bank6 or bank7, so we can know what the max SDRAM is. What are the purposes of other banks ??
What is the internal 1 GB ?? Or is it just a Slot Bank ??

Author:Cyanite0909 (cyanite)
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2008/3/20 05:58:28 pm

Other banks depend on how you want to use them. Generally, bank0 is used to connect to norflash. For other bank1, You need to renew your subscription, each bank has the corresponding chip select parameter ngcsx. This is the optimal solution for the two largest addresses in the bank, such as bank1 (ngcs1) you can access the network card. in any case, those banks are used for the charge function. however, the weekly dedicated IC that supports the host interface can go up.
In fact, the Bank 6, 7 does not need to use that large memory only when it uses bank6, so the bank 7 can also be set to the ROM/SRAM mode, you can use the weekly renewal function.

Author:Huah (Huah)
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2008/3/21 12:57:08 AM

There are some things you have done in sequence. The core of s3c2440a is a memory ARM920T, and its addressing
The blank space is 4G bytes (currently, the SOC large memory is almost the fixed address space of 4G bytes, 2 ^ 32 ).
With these fixed address spaces (currently all in physical address), design the chip engineering environment or company
This will allow us to use these spaces to specify the memory, memory, or flash to be used. Generally, we will
Let's look at the memory map first. What you should see is the memory map of Figure 5.1.
Only 1G bytes of 0x000000000000-0x3fffffff is specified, and table1.4 has other
The address space used.
Note that it is a fixed address space, not a memory space ***
Zookeeper has many protocol connection methods, such as UART, I2C, SPI, PCI,..., and message queue. Some of them use memory.
Interface to access the chip, such as some Ethernet chip, general USB device
Controller. In addition, the most important thing is Ram and flash.
The allocated memory interfaces generally include clock, chip select, address lines, data lines,
Read, write, and so on. Therefore, the SDRAM, nor, Nand, or pseudo-device is connected to an Ethernet CS8900.
Controller, it must have a positive message to access these chips, and the features of each segment are different,
A Bank indicates that you can set up a correct and reliable email feature to access a specific chip, so your bank 0 and
The messaging feature of bank 1 may be totally different, because the two different chips messaging features are completely different.
Message Queue features include high-speed memory interfaces used by SDRAM and low-speed memory Interfaces
Memory interface.
The correct mode of thinking is that you access the content of an actual memory location, and the SOC will follow the specifications of the SOC.
The chip select of the bank will be active at the time of the operation, and the trusted feature will
According to the settings of system registers, the most important step of booting is
Bank's credit features.
The chip uses that bank. It depends on the hardware design. There is no limit. If you use EVB,
Schematics will be included in the CD, and those who are working on the embedded system should learn to see it.
In general, the SOC considers its features when assigning a fixed address for each bank. In terms of s3c2440a,
The Bank 6 and 7 are used to release the SDRAM, so we need to take a test of the large space, and the actual usage depends on your
Product requirements, for example, an IP address sharer may be 8 MB of SDRAM, so it will not be used more, it is a cost,
In fact, both products will take the test of cost down, who does not want low costs can make the same amount of money, so you can see two
With the addition of banks, up to MB of SDRAM can be stored. Most of them will not be as big as they are, but they still need to be retained.
There are 4 GB space allocated, which is not very cost-effective. There is no extra cost for allocating large addresses.
For Pocket PC phone, if 128 MB is used, if the initial batch size is not large, it cannot be used.
Such products.
In fact, if memory bus is used for nand, generally only two address lines (for ale and CLE) are used ),
If the access time of NAND is 16 bits at a time, 8 bytes of address space will be used from memory,
The full access method of NAND is not a singleton of sending messages to address lines, so you can encrypt the corresponding content.
Content, there are some first-and later-related and Program There are also many types of NAND interfaces, which are not described here.
Using the ale and CLE methods. Some Soc have a single-node NAND controller, and the message queue does not pass through memory.
Interface, but the connection of zookeeper on the SOC. In order to use the controller (for example, ECC self-calculation,
Booting), we will use the login interface to connect with nand hosts, but you can still connect it
On the memory interface, you can use the NAND chip when the anti-positive signal is positive.
The ale/CLE messages with zookeeper are connected to the kernel. If you want to use NAND boot, you must also receive those messages.

Author:Huah (Huah)
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2008/3/21 01:13:29 AM

In addition, if you want to understand the related topics, you need to pay attention to the solution of the message queue.
For SDRAM, to be able to operate correctly, we need to follow the signal characteristics of the SDRAM chip and set the corresponding data,
That is, bankcon06 (0x481_1c), refresh (0x48000024), and banksize
(0x48000028), mrsrb6 (0x481_2c). Then the email will be executed according to these settings. When you
When you see the signal level, you should note that if 16 bits of SDRAM, access 0x3000_2468
1. For s3c2440a, the address is 0x3000_2468, but the email address lines
Only 0 0 0... (0 0 1 0) (0 1 0 0) (0 1 0) (1 0 0 ).
2. For SDRAM, its position is 0x00002468.
However, you may think that, however, the system works normally based on the match of the telecom signal.
It is consistent. If you have the chance to connect to the topics related to PCI, the same is true. Generally, your memory
The address on the PCI bus and the address on the PCI bus will not be the same. In the same way, the power level is the same.
In addition, the current arguments are physical addresses, which do not involve virtual addresses at all.
MMU and the virtual address has been expired, and the final transaction must be sent back to physical address to check the interface information.

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2008/3/21 10:37:53 AM

Thanks to everyone, yesterday I also understood the concepts of address map and memory interface.
I have a question: In SFR, most of the differences between the two Reg versions are 4 times? What are the special reasons? The hardware design is determined by the CS in SCH to use those banks ??
Zookeeper

Author:Huah (Huah)
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2008/3/22 12:18:56 AM

If it is 32 bits, It will be placed in the 4-bytes alignment location. It is convenient to see that 8 bits or 16 bits are like this.
The rows are also OK. For the UART OF Ti omap850, it is an 8 bits access, the UART
The Controller's registers are between bytes, that is, 1-byte alignment, but to Ti OMAP 2430,
In the same UART Controller, the Controller's register is 8 bits, but the position is a hop.
4 bytes.
In general, the SOC is also switched into a dynamic IP address, and the internal part also has a bus. The structure is more complex. Different data streams will have a bus
Arbitrator has address lines in the same way, so the same product and controller with the same function (same
UART, same as USB, etc.) normally, it is a single-region Region region. In the example of a dedicated OMAP, Ti omap850
That is, when bus A0 is connected to the A0 Of The UART (0, 1, 2) controller, but when it reaches OMAP 2430, it may be expected to be consistent
To 4-bytes alignment, so it becomes A0.
How the hardware design considers the bank and determines
1. Features: For s3c2440a, only bank6 or bank7 can be stored in SDRAM.
2. boot-up function: A physical SOC may have a booting mode (depending on the configuration pins
Consider pulling high or low), in the case of s3c2440a, if you want to use nor boot, put it in bank0
3. System vector address: For arm, core before arm11, interrupt/exception, etc.
The location must be 0x00000000 (when there is virtual address, it is virtual address
0x00000000). If the ARM core is based on protection unit, virtual
Address. You can choose whether or not 0x0 has 0000 for the nor or SDRAM. It must be follow.
This SOC can support. Because s3c2440a uses ARM920T and has MMU
The virtual address can be handled. If it is, it uses arm940t, only
Proteciton unit, to map 0x00000000 to SDRAM, it must be set by Remap.
When 0x00000000 is remap to SDRAM bank0, 0x40000000 is remap to SDRAM
Bank1, so if you want to put system vector address in a single SDRAM, you can only
Upload to SDRAM bank0.
4. Pin merge multiplexers: Generally, all functions contained in the SOC cannot be used at the same time. One of the reasons is that
The more limited pin values, the larger the number of Pin values, and the higher the difficulty of construction.
According to the different application types of the SOC, it is suggested that pin numbers be shared.
When the interface information is sent, other interfaces cannot be used at the same time. When we survey SOC, we will be very careful
In general, the selection of the bank is generally from a small
For initial selection, CSX is usually reserved. In addition, special email settings may only have the highest priority.
5. helper NAND Controller: it may only work with special banks, but it does not work with s3c2440a.
There is an established ale/CLE, so you need to use the NAND controller, Please access your computer.
The above only lists some of the things I think of. In fact, there may be a lot of things I didn't think.
In addition, most of them directly participate in reference design (s), and there is a license for a bill.