S5PC100 Watchdog timer (source code interpretation) _S5PC100 processor

From: s5pc100 Watchdog timer Author: Ms. Yang, huaqing visionary embedded college lecturer.

Watchdog (watchdog) timer and PWM timing function are not the same. It is characterized by the need to constantly accept signals (some external watchdog chip) or reset the count value (such as S5PC100 watchdog Controller), keep the count value is not 0. Once the signal has not been received for a period of time, or the count is 0, the watchdog will issue a reset signal to reset the system or cause an interruption. (Extended reading: Pulse width modulation timer)

The role of watchdog is to make the system reset within a certain time interval after the micro controller is disturbed into the wrong state. Therefore, the watchdog is an effective measure to ensure the long-term, reliable and stable operation of the system. At present, the watchdog timer is integrated into most embedded chips to improve the reliability of system operation.

The watchdog of the S5PC100 processor is the reset operation for the microprocessor when the system is disturbed (such as noise or system error), or it can be used as a general-purpose 16-bit timer to request the interrupt operation. The watchdog timer generates 128 PCLK cycle reset signals. The main features are as follows:

16-bit timer for general interrupt mode.

When the counter is reduced to 0 (overflow), a reset signal of 128 PLK cycles is generated.

The function block diagram of the watchdog timer is shown in Figure 10-5.

Fig. 1 The function diagram of the watchdog of S5pc100

1. Watchdog software program design process

Because the watchdog is a reset or interrupted operation of the system, it does not require a peripheral hardware circuit. To implement the watchdog function, you only need to operate on the watchdog's Register group, that is, the watchdog's control Register (WTCON), watchdog data Register (WTDAT), watchdog Count Register (wtcnt).

The general process is as follows.

(1) Set up watchdog interrupt operation including global interrupt and watchdog interrupt to enable and watchdog interrupt vector definition, if only for the reset operation, this step can not be set.

(2) The setting of the watchdog control Register (WTCON) includes setting the Prescaler frequency proportional factor, the frequency divider value, the interrupt enabling and the reset enabling etc.

(3) settings for watchdog data registers (WTDAT) and watchdog count Registers (wtcnt).

(4) Start watchdog timer.

2. Definition of watchdog Register

/*
Definition of *watchdog Registers
*/
typedef struct {
unsigned int wtcon;
unsigned int wtdat;
unsigned int wtcnt;
unsigned int wtclrint;
}WDT;
#define WDT (* (volatile WDT *) 0xea200000)

3. Initialization of watchdog registers

void Wdt_init ()
{
WDT. wtcnt = 0x277e;
WDT. Wtdat = 0x277e;
WDT. Wtcon = (1<<0) | (3<<3) | (1<<5) | (255<<8);
66MHZ Prescaler frequency 255 Get 255824HZ and then do 128 frequency divider get f = 2022HZ
Data * 1/f = 5 delay 5 seconds to get data = 0x277e
}

4. Preparation of watchdog main program

#include "S5pc100.h"
int main ()
{
int i;
GPG3. Gpg3con = (~ (0xf<<4) &gpg3. Gpg3con) | (0X1<<4);
GPG3. Gpg3dat = 0x2;
Light LEDs to test the reset function of the watchdog
Wdt_init ();
while (1);
return 0;
}

5. Observation of experimental results

After the program runs for 5 seconds, the LEDs will go out because the CPU at this time has been reset.

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