S5PV210 Development Series five _SD card driver implementation

S5PV210 Development Series five SD card driver implementation

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SD card (Secure Digital Memory card) has the advantages of small size, large capacity, fast data transmission, pluggable, security, etc., which are widely used in portable devices. For example, as a memory card for digital camera, as a mobile phone, tablet multimedia expansion card with the TF card (micro SD). The author here on the s5pv210 SD card driver implementation as a simple introduction.

1. SD Card Overview

SD card technology is developed on the basis of the MMC card, the size of the same as the MMC card, just 0.7mm thicker than the MMC card, so the SD device can recognize and access the MMC card. The SD card interface, in addition to retaining the 7-pin MMC card, also adds 2 pins on both sides, as a data line, in order to improve the transmission rate by turning the transmission mode from serial to parallel. At this time the specification is sd1.0 version, the maximum capacity only to 4GB. In order to follow up on the replacement of products, the SD association released the next generation SD card specification sd2.0 with larger capacity and faster storage in 06. The specification redefined the speed level of the SD card, divided into three gears: Class 2, 4, 6, corresponding to the write speed 2mb/s, 4mb/s, 6mb/s. According to the card capacity is divided into standard cards (less than 2GB) and high-capacity cards (2GB~32GB), the current application of the SD card on the market is mostly sd2.0 version of the card. In order to make the memory card more mini, through the SD card specification standard, but also derived the MINISD card and micro SD card, these cards are smaller than the standard SD card size, through the SD card can be used as a general SD card. In particular, micro SD card, can be regarded as the smallest memory card, ultra-small volume can greatly save the interior design of consumer electronics space, the basic current Android phones are selected micro SD card as a multimedia expansion memory card. With the progress of science and technology, SD2.0 standard SD card is also gradually unable to meet the needs of the application, in 10 SD Association released a new SD3.0 specification, the specification defines SDXC and UHS, and increased Class10, capacity range of 32GB~2TB. While the SDXC card still needs to wait for its price to fall further, the SD4.0 specification has begun to develop in tension, which is beyond the scope of this article.

2. SD Card Driver Authoring

The SD card supports a total of three transmission modes: SPI mode, 1-bit SD mode, and 4-bit SD mode. All SD cards must support the older SPI/MMC mode, which supports a slow four-wire SPI interface, enabling many microcontrollers to read and write SD cards via the SPI or analog SPI interface. Because the s5pv210 has an SD card host controller, and supports the sd2.0 standard, here only analysis of 4-bit SD mode, sd2.0 and sd1.0 version of the SD card driver implementation, sd2.0 version of SD card, MMC card, SPI mode read and write SD card is not applicable in this article.

sd2.0 standard defines the physical layer correlation specification and the host controller specification, the SD card driver writing must refer to these two specifications, mainly is the s5pv210 in the SD host controller programming, this part to all has the SD host controller microprocessor to be suitable, only registers the name difference. There are only a few important processes or concepts to be explained in accordance with the SD2.0 specification, which are implemented in the SD driver module.

2.1. SD card initialization and identification process

When the SD card is power-up, it will enter the idle state, at which time the SD card is 1-bit SD mode. By pulling down the CS line will enable SD into the SPI mode (no longer discussed in the scope), in SD mode card initialization and identification process is shown in Figure 2.1.1, the steps are as follows:

1) Send CMD0 software to reset all the cards to the idle state.

2) Send CMD8 to check whether the card supports the host voltage (2.7v~3.3v), this command is defined above sd2.0, if not received a reply signal, it may be sd1.0 or MMC card, if the card is received back signal, the sd2.0 version of the card, jump to step 5

3) CMD8 did not receive a response signal, can further send ACMD41 (cmd55+cmd41), the parameter HCS bit 0 (non-high capacity card), if there is no reply signal, the description is an MMC card or other unrecognized card, can further send CMD1 determine whether the MMC card (no longer analyzed here)

4) ACMD41 can receive a reply, and from the reply to determine the SD card is ready, you can determine this is the sd1.x version of the card, if the reply indicates that the SD card is not ready, you need to repeat the ACMD41 waiting card ready, can be timed out (card has been busy) to determine the card does not support the host voltage, This indicates that the card is not available. After judging the sd1.x card, skip to step 9.

5) CMD8 has a reply to sd2.0 above card, from the reply to determine whether the card can work under the voltage, can not think that the card is not available.

6) Reply to determine the card can be 2.7v~3.3v voltage operation, further send ACMD41 (cmd55+cmd41), the parameter HCS bit 1 indicates that the host supports high-capacity cards

7) Check ACMD41 card reply busy flag, if the card is in a busy state, then send ACDM41 repeatedly until the card is ready, can be considered to be unavailable by time-out (card has been busy state).

8) ACMD41 reply to prepare, and then check the response in the CCS bit, the bit is 1 description is sd2.0 high capacity SDHC card, if 0, it is sd2.0 standard capacity card.

9) After identifying the sd1.x, sd2.0 standard card or sd2.0 high-capacity card, the card enters ready state. Further through the CMD2 request card to send its CID (Card identification), this time the card into the identification state.

10) After the card in the identification state, send CMD3 Request card issued a 16-bit new relative address (RCA), after the host and the card point-to-point communication will be the RCA address to proceed, this time the card into the stand-by state.

11) At this point, the card initialization and identification process is over, the card enters the data transmission mode (data transfer modes)

Figure 2.1.1. SD card initialization and identification process

2.2. Data transfer Mode

SD card is a very typical state machine, each state will only respond to a specific command in a state, do not attempt to send a command in a state that is not supported by the state, the SD card will not respond to the command, the command will only time out. You should change the state or wait for the State migration to complete before sending the corresponding state command through a specific trigger condition. 2.2.1, to write a block of data to the SD card, in the case of stand-by state, you must select the card through CMD7, let the card into the transfer state, and then send a CMD24 single-block write command, and then send a piece of data, the card into the programming state, At this point, if you send the CMD24 immediately after the single block write will not succeed, you must wait for the SD card to finish programming, from the programming state to return to the transfer state to receive the next block write command again. Similarly, in the transfer state to obtain the Card-specific Data (CSD) through the CMD9, the card must be de-selected through CMD7, when the card enters the stand-by state, the card information can be obtained through CMD9.

Figure 2.2.1. SD Card data transfer mode

2.3. Host controller initialization of the card

SD Card host controller can be based on the SD2.0 specification card initialization and identification process for card initialization, host controller register settings mainly have the following points, the specific implementation can refer to Hsmmc_init () this initialization function.

1) Set the function pin, configure the corresponding PIN to the SD interface with pin

2) Set the SD card clock in the 100K~400K,SD card in the identification phase must be accessed with a slow clock

3) According to the card initialization process given by the specification, send the corresponding command and process the reply, the card enters the stand-by state after the success.

4) by sending CMD7 Select card, so that the card into the transfer state, because most of the card operations such as reading, writing, erasing, etc. are in this state down, the card is fully ready to receive read and write commands.

5) Set the SD card clock to a higher value, SD card support up to 25M clock, for sd1.1 above standard, can check whether the card supports high-speed mode, if the support switch to high-speed mode, the highest support 50M, the higher the frequency, the faster the data transfer rate

6) by ACMD6 (CMD55+CMD6) to set the SD mode of the bit width for the 4,SD card is initialized after the default is 1 line width, more data lines will have greater bandwidth, data transmission rate of the highest 12.5mb/s (25M, 4 lines) or 25mb/s (50M, 4 lines).

7) Send CMD16 set block length, for standard cards, can be CMD16 to set the Block command (such as Block read, block write) the length of the block (in bytes), can achieve byte read and write, but for high-capacity cards This command will be ignored, high-capacity card a block length is fixed 512 bytes. A block length of 512 bytes is usually set via CMD16. This is the completion of the card initialization.

int hsmmc_init (void)

{

int32_t Timeout;

uint32_t capacity;

uint32_t i;

uint32_t OCR;

uint32_t Temp;

uint8_t switchstatus[64];

SD_SCR SCR;

uint8_t csd[16];

uint32_t c_size, C_size_multi, Read_bl_len;

Setting the interface pin configuration for the HSMMC

#if (Hsmmc_num = = 0)

Channel 0,gpg0[0:6] = CLK, CMD, CDn, Dat[0:3]

Gpg0con_reg = 0x2222222;

Pull up Enable

Gpg0pud_reg = 0X2AAA;

Gpg0drv_reg = 0X3FFF;

Channel 0 Clock src = SCLKEPLL = 96M

Clk_src4_reg = (Clk_src4_reg & (~ (0xf<<0))) | (0x7<<0);

Channel 0 Clock = SCLKEPLL/2 = 48M

Clk_div4_reg = (Clk_div4_reg & (~ (0xf<<0))) | (0x1<<0);

#elif (Hsmmc_num = = 1)

Channel 1,gpg1[0:6] = CLK, CMD, CDn, Dat[0:3]

Gpg1con_reg = 0x2222222;

Pull up Enable

Gpg1pud_reg = 0X2AAA;

Gpg1drv_reg = 0X3FFF;

Channel 1 Clock src = SCLKEPLL = 96M

Clk_src4_reg = (Clk_src4_reg & (~ (0xf<<4))) | (0X7<<4);

Channel 1 Clock = SCLKEPLL/2 = 48M

Clk_div4_reg = (Clk_div4_reg & (~ (0xf<<4))) | (0X1<<4);

#elif (Hsmmc_num = = 2)

Channel 2,gpg2[0:6] = CLK, CMD, CDn, Dat[0:3]

Gpg2con_reg = 0x2222222;

Pull up Enable

Gpg2pud_reg = 0X2AAA;

Gpg2drv_reg = 0X3FFF;

Channel 2 clock src = SCLKEPLL = 96M

Clk_src4_reg = (Clk_src4_reg & (~ (0xf<<8))) | (0X7<<8);

Channel 2 Clock = SCLKEPLL/2 = 48M

Clk_div4_reg = (Clk_div4_reg & (~ (0xf<<8))) | (0X1<<8);

#elif (Hsmmc_num = = 3)

Channel 3,gpg3[0:6] = CLK, CMD, CDn, Dat[0:3]

Gpg3con_reg = 0x2222222;

Pull up Enable

Gpg3pud_reg = 0X2AAA;

Gpg3drv_reg = 0X3FFF;

Channel 3 clock src = SCLKEPLL = 96M

Clk_src4_reg = (Clk_src4_reg & (~ (0xf<<12))) | (0X7<<12);

Channel 3 Clock = SCLKEPLL/2 = 48M

Clk_div4_reg = (Clk_div4_reg & (~ (0xf<<12))) | (0X1<<12);

#endif

Software reset for all

__REGB (Hsmmc_base+swrst_offset) = 0x1;

Timeout = 1000; Wait Max Ten MS

while (__REGB (Hsmmc_base+swrst_offset) & (1<<0)) {

if (timeout== 0) {

return-1; Reset Timeout

}

timeout--;

Delay_us (10);

}

Hsmmc_setclock (400000); 400k

__REGB (Hsmmc_base+timeoutcon_offset) = 0xe; Maximum timeout time

__REGB (Hsmmc_base+hostctl_offset) &= ~ (1<<2);//normal Speed mode

Clear normal interrupt status flag

__REGW (Hsmmc_base+norintsts_offset) =__REGW (Hsmmc_base+norintsts_offset);

Clear Error interrupt Status flag

__REGW (Hsmmc_base+errintsts_offset) =__REGW (Hsmmc_base+errintsts_offset);

__REGW (Hsmmc_base+norintstsen_offset) = 0X7FFF; [14:0] Interrupt State enable

__REGW (Hsmmc_base+errintstsen_offset) = 0x3ff; [9:0] Error interrupt State enable

__REGW (Hsmmc_base+norintsigen_offset) = 0X7FFF; [14:0] Interrupt signal enable

__REGW (Hsmmc_base+errintsigen_offset) = 0x3ff; [9:0] Error interrupt signal enable

Hsmmc_issuecommand (CMD0, 0, 0, cmd_resp_none); Reset all cards to idle state

Cardtype = unusable; Card type initialization is not available

No reply, mmc/sd V1.x/notcard

if (Hsmmc_issuecommand (CMD8, 0X1AA, 0, cmd_resp_r7)) {

for (i=0;i<100; i++) {

Hsmmc_issuecommand (cmd55,0, 0, CMD_RESP_R1);

CMD41 has reply note for SD card

if (! Hsmmc_issuecommand (CMD41, 0, 0, CMD_RESP_R3)) {

OCR (operating condition register) value for the reply

OCR = __reg (Hsmmc_base+rspreg0_offset);

Does the power on the card complete the power-up process, busy

if (ocr& 0x80000000) {

Cardtype= SD_V1; Correctly identify the SD v1.x card

Debug ("SDcard version 1.x is detected\r\n");

Break

}

} else {

MMC card recognition

Debug ("Mmccard is not supported\r\n");

return-1;

}

Delay_us (1000);

}

} else {//SD v2.0

Temp =__reg (Hsmmc_base+rspreg0_offset);

Determine if the card supports 2.7~3.3v voltage

if (((temp&0xff) = = 0xaa) && (((temp>>8) &0xf) = = 0x1) {

OCR = 0;

for (i=0;i<100; i++) {

OCR |= (1<<30);

Hsmmc_issuecommand (cmd55,0, 0, CMD_RESP_R1);

Hsmmc_issuecommand (CMD41,OCR, 0, CMD_RESP_R3); Reday State

OCR =__reg (Hsmmc_base+rspreg0_offset);

Does the power on the card complete the power-up process, busy

if (ocr& 0x80000000) {

Determine whether the card is a standard card or a high-capacity card

if (ocr& (1<<30)) {

Cardtype= SD_HC; High-capacity cards

Debug ("Sdhccard is detected\r\n");

} else {

Cardtype= Sd_v2; Standard Card

Debug ("Sdversion 2.0 standard card is detected\r\n");

}

Break

}

Delay_us (1000);

}

}

}

if (Cardtype = = SD_HC | | Cardtype = = SD_V1 | | cardtype== sd_v2) {

Request Card Send CID (Card ID register) number, enter ident

Hsmmc_issuecommand (cmd2,0, 0, CMD_RESP_R2);

Request Card release new RCA (card relative address), stand-by status

Hsmmc_issuecommand (cmd3,0, 0, CMD_RESP_R6);

Get card relative address from card reply

RCA = (__reg (hsmmc_base+rspreg0_offset) >>) & 0xFFFF;

Select the tagged card, transfer status

Hsmmc_issuecommand (cmd7,rca<<16, 0, CMD_RESP_R1);

HSMMC_GET_SCR (&SCR);

if (SCR. Sd_spec = = 0) {//SD 1.0-SD 1.01

Version 1.0 doesn ' t support switching

Hsmmc_setclock (24000000);//Set sdclk = 48M/2 = 24M

} else {//SD 1.10/SD 2.0

Temp = 0;

for (i=0;i<4; i++) {

Switch check

if (hsmmc_switch (0, 0, 1, switchstatus) = = 0) {

Group 1, Function 1 high-speed bit 273

if (! ( SWITCHSTATUS[34] & (1<<1)) {

Thehigh-speed function is ready

Group, function 1 high-speed support bit 401

if (Switchstatus[50] & (1<<1)) {

High-speed is supported

if (Hsmmc_switch (1, 0, 1, switchstatus) = = 0) {//Switch

function switch in Group 1 is OK?

if ((switchstatus[47]& 0xf) = = 1) {

Result of the switch high-speed in function Group 1

Debug ("Switchto High speed MODE:CLK @ 50m\r\n");

Hsmmc_setclock (48000000);//Set sdclk = 48M

Temp= 1;

}

}

}

Break

}

}

}

if (Temp ==0) {

Hsmmc_setclock (24000000);//Set sdclk = 48M/2 = 24M

}

}

if (! Hsmmc_setbuswidth (4)) {

Debug ("Setbus width error\r\n");

return-1; Error in bit width setting

}

This time the card should be in transfer state

if (hsmmc_getcardstate () = = Card_tran) {

Set the block length to 512 bytes

if (! Hsmmc_issuecommand (CMD16, 0, cmd_resp_r1)) {

__REGW (Hsmmc_base+norintsts_offset) = 0xFFFF; Clear Interrupt Flag

HSMMC_GET_CSD (CSD);

CSD v1.0->sd v1.x, SD v2.00 Standard

if ((csd[15]>>6) = = 0) {

read_bl_len= csd[10] & 0xf; [83:80]

C_size_multi= ((csd[6] & 0x3) << 1) + ((Csd[5] & 0x80) >> 7);

C_size = ((int32_t) (csd[9]&0x3) <<) + ((int32_t) csd[8]<<2)

+ (CSD[7]>>6); [73:62]

capacity= (c_size + 1) << ((C_size_multi + 2) +

(read_bl_len-9)); Block (in bytes)

} else {

C_size = ((csd[8]&0x3f) << + (csd[7]<<8) + csd[6];

The card capacity is byte (c_size+1) *512kbyte, with 1 sectors in Byte, the number of sectors of the card is

Capacity= (c_size+1) << 10;//block (byte)

}

Debug ("Cardinitialization succeed\r\n");

Debug ("capacity:%ldmb\r\n", Capacity/(1024*1024/512));

Return 0;//initialization succeeded

}

}

}

Debug ("Card initialization failed\r\n");

return-1; Card Work exception

}

2.4. Sending of HOST commands

The SD specification makes detailed requirements for command package format, reply packet, and data transmission mode. Although the SD card host controller can help us package the command, unpack the reply, generate the CRC, and output the corresponding timing on the SD bus. We still need to tell the SD card host controller to send the command, the parameters of this command, whether the command is sent after the use of the data line, SD card reply type. These settings are implemented via the host controller Cmdreg register. The main points are as follows, the specific implementation can refer to Hsmmc_issuecommand () This command send function.

1) When the command is sent, check that the command line is already in use and, if so, wait for the command being sent to send the command.

2) If the command reply will be with a busy signal (such as R1b Reply), you need to check whether the data cable has been used, if, wait for the data line is idle, with the busy reply command sent, the SD card will pull down the dat[0] line indicates that the SD card is busy, the data cable is not available.

3) write the command parameters to argument in this register

4) Set the command value in Cmdreg [13:8]

5) Set whether to use the data line, such as Block read, block write, and so on after the command sent, will be transmitted on the information line, and other data do not need to transfer the command do not set the use data line cmdreg[5]

6) Set the reply type of SD card, most of the commands will reply to the host after the SD card responds correctly (R1-R7,R1B), please refer to the SD card specification for each command corresponding reply type. The reply type may be 136 or 48, if the reply contains a CRC or command value feedback, and if it is included, tell the host controller to check that the appropriate CRC or command value feedback is correct in the reply to determine the transmission is correct. When the Cmdreg is set up, the host controller sends a command and receives a set length reply and checks the CRC according to the settings, and the command value feedback is correct (if the reply contains CRC or command value feedback)

7) Wait for the command to complete, check the interrupt status bit norintsts[15] to determine if the command has an error, and if there is no error and the Norintsts[0] command completion bit is 1, the command is sent successfully. Other circumstances indicate that the command failed to send successfully.

2.5. Drive Module Interface

Usually for an SD card driver module, at least implement card initialization, block read, block write these three interface functions. This is usually the most basic underlying disk interface implementation of a filesystem. Refer to the implementation of the three functions of Hsmmc_init (), Hsmmc_readblock () and Hsmmc_writeblock ().

3. Appendix

Hsmmc.rar, contains SD card driver module to implement Hsmmc.c/hsmmc.h.

Http://pan.baidu.com/s/1nsJx0

Copyright NOTICE: This article for Bo Master original article, without Bo Master permission not reproduced.

S5PV210 Development Series five _SD card driver implementation