S5PV210 Hardware Structure

S5PV210 Hardware Structure

This chapter describes the hardware structure of the s5pv210, including the s5pv210 microprocessor, GPIO interface, PWM timer, DMA controller, UART serial interface, SPI interface, IIC bus interface and ADC and touch screen interface. The application examples and drivers of the interface are introduced.

The s5pv210 is a 32-bit microprocessor with low power features that provide high-performance microprocessor solutions for mobile devices and general applications. It integrates the arm CORTEX-A8 Core, implements the ARM architecture v7a, and supports peripheral devices. Its architecture includes: microprocessor, memory subsystem, multimedia, audio subsystem, security subsystem, interface, System peripherals.

Gpio Private Register: Port Group control Register, port Group Gpao Control Register, Port Group GPA1 Control Register, GPIO interrupt control register.

The PWM (pulse width modulation) timer is used to generate internal interrupts to the arm subsystem, and the s5pv210 consists of 5 32-bit PWM timers.

The s5pv210 supports direct memory access (DMA Controller) because: 1. Memory-memory conversion; 2. Peripheral device to memory transfer.

The s5pv210 universal asynchronous receive/Send device (UART serial interface) provides four independent asynchronous serial input/output (I/O) ports, and the UART controller can generate an interrupt or DMA request between the CPU and the UART to transmit data. It contains programmable baud rate, IR receive/send, insert one or two stop bits, 4-8-bit data width, and parity. Each UART includes a baud rate generator, a transmitter, a receiver, and a control unit. UART operations include data transfer, receiving, interrupt generation, baud rate generation, loopback mode, infrared mode, and automatic flow control.

The SPI interface of the S5PV210 communicates with various peripherals using transmitted serial data. The SPI consists of two 8/16/32-bit shift registers for receiving and transmitting data. The SPI has two modes, the main mode and the slave mode.

The S5PV210 processor supports a multi-master IIC bus interface with four modes of operation: Primary control transmit mode, master control receive mode, slave transmit mode, and slave receive mode.

ADC (Analog-to-digital converter) and touch-screen interface: The touchscreen interface controls the selection of the touch-screen contacts for XY-coordinate conversion, which includes touch contact control logic and ADC interface logic with interrupt-generating logic.

S5PV210 Hardware Structure