Sampling time sampling frequency calculation of ADC sampling period

ADC conversion is the input analog signal volume, the microcontroller converted to digital volume. Reading the number must wait for the conversion to complete, the completion of a channel reading is called the sampling period. Sampling period generally = conversion time + read time. The conversion time = sampling time + 12.5 clock cycles. The sampling time is the time you tell the STM32 sampling analog through the register, the longer the setting the more accurate

Determination of sampling frequency for a STM32 ADC

1. :

Take a look at some data to determine the ADC clock:

(1), the adcclk clock provided by the clock controller is synchronized with the PCLK2 (APB2 clock ) . The CLK Controller provides a dedicated programmable prescaler for the ADC clock.

(2) In general, the PCLK2 clock is set to the same as the system clock in the program

/* HCLK = SYSCLK */

Rcc_hclkconfig (RCC_SYSCLK_DIV1);

/* PCLK2 = HCLK */

Rcc_pclk2config (RCC_HCLK_DIV1);

/* PCLK1 = HCLK/2 */

Rcc_pclk1config (RCC_HCLK_DIV2);

(3) A dedicated programmable prescaler for the ADC clock is available in the Clock Configuration register (RCC_CFGR)

Bit 15:14 adcpre:ADC Prescaler

Software settings to determine the ADC clock frequency

xx:PCLK2 2 as ADC clock

PCLK2:4 -divided as ADC clock

6:PCLK2 as ADC clock

One:PCLK2 8 divided as ADC clock

We can set it up for example:

/* ADCCLK = PCLK2/4 */

Rcc_adcclkconfig (RCC_PCLK2_DIV4);

There is also an ADC clock enable setting

/* Enable ADC1, ADC2 and GPIOC clock */

Rcc_apb2periphclockcmd (RCC_APB2PERIPH_ADC1 | RCC_APB2PERIPH_ADC2 |

RCC_APB2PERIPH_GPIOC, ENABLE);

(4) 16.7 programmable channel sampling time

The ADC uses several ADC_CLK cycles to sample the input voltage, and the number of sample cycles can be

The smp[2:0] bit in the adc_smpr1 and adc_smpr2 registers is changed. Each channel can be

Different time samples.

The total conversion time is calculated as follows:

TCONV (conversion time) = sampling time + 12.5 Cycles

For example:

When sampling time for Adcclk=14mhz and 1.5 cycles:

TCONV = 1.5 + 12.5 = Cycle = 1μs

smpx[2:0]: Select the sampling time for channel x

These bits are used to independently select the sampling time for each channel. The channel select bits must remain constant during the sampling period.

£ º1.5 cycle :41.5 cycle

001:7.5 Cycle 101:55.5 Cycle

010:13.5 cycle :71.5 Cycle

011:28.5 cycle 111:239.5 Cycle

Note:

The analog input channels of the –adc1 and channel, respectively, are connected to the temperature sensor and the Vrefintinside the chip.

The analog input channel of the –adc2 is connected to VSSwithin the chip and the channel.

2. The detailed analysis is as follows:

(1) Our input signal is 50Hz (period is 20ms), initially set to 1 cycle 200 sampling points, (note: a period of at least 20 points, that is, the sampling rate is at least 1k), every 2 sampling point interval is 20ms/200 = us

ADC Programmable Channel Sampling time we select the minimum 1.5-cycle period, the ADC sample period of one period is the size of

100us/1.5=66us. The ADC clock frequency is 1/66us =15 KHz.

ADC Programmable Channel Sampling time we choose a 71.5 cycle, then the ADC sample cycle size is

(100us/71.5). The ADC clock frequency is 7.15MHz.

(2) Next we need to determine the system clock: We use a 8M Hz external crystal Clock Source (HSE), estimated by the PLL multiplier PLL multiplier factor of 2, the integer multiples, the maximum of MHz. To improve the efficiency of data calculation, we set the system clock to 72MHz, (PLL 9 times octave). Then pclk2=72mhz,pclk1=36mhz;

We have a dedicated programmable prescaler for the ADC clock by setting the clock configuration register (RCC_CFGR), which divides the PCLK2 8 as the ADC clock, then the ADC clock frequency is 9MHz

From the manual: ADC Conversion Time:

stm32f103xx Enhanced: TheADC clock is 1μs at 56MHz (TheADC clock is 72MHz 1.17μs)

(3) from the above analysis: not very corresponding, we re-adjust the above content, proposed the following two sets of solutions:

Scenario One: Our input signal is 50Hz (period is 20ms), initially set to 1 cycle 2500 sampling points, (note: A cycle of at least 20 points, that is, the sampling rate is at least 1k), every 2 sample point interval is 20ms/2500 = 8 US

ADC Programmable Channel Sampling time we select the 71.5 cycle, the ADC sample period of one cycle size is

8us/71.5 . The ADC clock frequency is approximately 9 MHz.

When the PCLK2 8 is divided as the ADC clock, the ADC clock frequency is 9MHz

Scenario Two: Our input signal is 50Hz (period is 20ms), initially set to 1 cycle of the sampling point, (note: A cycle of at least 20 points, that is, the sampling rate is at least 1k), every 2 sampling point interval of 20ms/1000= us

ADC Programmable Channel Sampling time we select the 239.5 cycle, the ADC sample period of one cycle size is

20us/239.5 . The ADC clock frequency is approximately a few MHz.

When the PCLK2 6 is divided as the ADC clock, the ADC clock frequency is 12MHz

Sampling time sampling frequency calculation of ADC sampling period