Sar adc: One-Step approximation register (SAR) ADC)

1. In order to implement the binary search algorithm, the N-bit register is first set to the intermediate scale (that is, 100... 00, and MSB is set to 1 ). In this way, the DAC output (vdac) is set to vref/2, and vref is the reference voltage provided to the ADC. Then, compare and determine whether vin is smaller than or greater than vdac. If Vin is greater than vdac, the MSB of the comparator output logic is 1 or 1, and the N-bit register is 1. Conversely, if vin is smaller than vdac, the comparator output logic is low and the MSB of the N-bit register is 0. Then, the SAR control logic is moved to the next position, and the bit is set to a high level for the next comparison. This process continues until LSB. After the above operation, the conversion is completed, and the N-bit conversion result is stored in the register.

Sar adc: One-Step approximation register (SAR) ADC)