Scan Design Rules

In order to design a scan designer better, some scan design rule must follow.

1) tristate bus must keep bus contention in shift mode;

2) bidirectional IO port in shift mode, force must be in input or output;

3) gated clock in shift mode, you must ensure the Enable;

4) derived clock in shift and capture mode, it is best to keep bypass;

5) Combinational's feedback, in shift and capture mode, should break;

6) Async Set/reset, under Shift and capture mode, it is best to use the external pin;

7) Clock drive data, in shift and capture mode, it is best to block;

8) floating buses, in shift and capture mode, increase bus keeper;

TriState buses:

The ATPG can guarantee that no two drive controls a bus in capture mode, but in shift mode,

There is no such guarantee, so it is required that the bus contention unchanged in shift mode.

And a bus without pull-up/pull-down/bus-keeper will also lead to fault coverage loss, because a floating bus

is unpredictable and cannot be tested for Stuck-at 1. So Pull-up/pull-down/bus-keeper's bus recommended design.

Bidirectional IO Port:

In a capture operation, bidirectional IO is specified as Input/output, but on shift operation,

Need extra control.

Gated Clock:

The Enable port of clock gate cannot be changed more than once between 0 and 1 under Shift mode.

Can be controlled using SE or TM signals.

Derived Clock:

A derived clock is defined from a storage element and a clock generator (pll,frequence divider,pluse generator)

During the whole test process, these clock must be bypass.

Combinational Feedback Loops:

When the number of inversion is odd, the output forms oscillation,

When the number of inversion is even, the output forms sequential behavior,

In the process of test, you need to ensure that the value in loop is controlled, so you need to pick up love like logic:

Async Set/reset Signals:

Async Set/reset cannot be controlled directly by primary input and may affect the proper operation of shift data, so it is required, in shift operation

, these signals are inactive by force.

The use of TM signals will cause these reset/set signals to not be tested during test,

Using the SE signal may cause competition between these set/reset clock.

Scan Design Rules