Second, state machine

1, the role of state machine? What is it?

State machines, as the name implies, are used to describe state. The perfect point is under the same clock. More accurately, it is a VERILOGHDL programming idea.

For example, each of our systems can be divided into several states, such as: Start, initialize, run, State 1, State 2, State 3, State 4, end.

2, State machine structure 1) output <= input about + current status

2) Output <= current status

3) Pipeline Register <= output <= output + current status

3, State machine Verilog Program

The behavior of a system or an object or the state of a device, we can be divided into several states, then we can draw a state diagram, of course, it is not possible to all States are like this, but the big dome small different. The output here is expressed in K1,k2, which represents what behavior our system will take when this state is used.

　　

1) General form of State machine program (usingGray Code）

Module FSM (clk,rst,a,k1,k2,state);

Input clk,rst,a;

Output K1,K2;

OUTPUT[1:0] State;

Reg K1,K2;

REG[1:0] State;

Parameter idle=2 ' b00,//idle

Start=2 ' B01,

Stop=2 ' B10,

Clear=2 ' B11;

[Email protected] (Posedge CLK)

if (!rst)

Begin

state<=idle;

k2<=0;

k1<=0;

End

Case (state)

Idle

if (a) Begin State<=start;k1<=0;end

ELSE BEGIN State<=idle;k2=0;k1=0;end

Start

if (!a) state<=stop;

else state<=stop;

Stop

if (a) Begin state<=clear; K2<=1;end

ELSE BEGIN Stste<=stop;k2<=0;k1<=0;end

Clear

if (!a) begin State<=idle;k2<=0;k1<=1;end

ELSE BEGIN State<=clear;k2<=0;k1<=1;end

Default

State<=2 ' bxx;

Endcase

Endmodule

2) withSingle Hot CodeRepresents the state machine

Parameter idle=4 ' b0000,

Start=4 ' b0100,

Stop=4 ' b0010,

Clear=4 ' b0001;

It's called a hot code, you know.

3)output <= Status value(state value directly as output) for high-speed state machine, because save time, save device, delay time is small

state<=start;　　............ state<=stoptoclear; ................ state=idle;

4) Multi-input state machine for large and complex designs, using always

Each clock produces a change in state

[Email protected] (Posedge CLK)

if (!rst)

state<=idle;

Else

state<=nextstate;

Generating the combined logic of the next state

[Email protected] (State or a)

Case (state)

Idle

if (a) Nextstate=start;

else Nextstate=idle;

Start

if (!a) nextstate=stop;

else Nextstate=start;

Stop

if (a) nextstate=clear;

else Nextstate=stop;

Clear

if (!a) Nextstate=idle;

else nextstate=clear;

Default

nextstate=2 ' bxx;

Endcase

Combined logic for generating output k1

[Email protected] (State or rest or a)

if (!rst)

k1=0;

Else

if (state==clear&&!a)

K1=1;

Else

k1=0;

Combinatorial logic for generating K2

[Email protected] (State or RST or a)

if (!SRT)

k2=0;

Else

if (state==stop&&a)

K2=1;

Else

k2=0;

4. Summary　　

Different types of state machines have different advantages.

Second, state machine