Sequence Detection 101 state machine Implementation

Module Jiance #

(
Parameter Cnt_num = 12500000
)

(Clk,rst_n,data, clk_1hz,out);
Input clk,rst_n,data;
Output Reg out,clk_1hz;
reg [1:0] cstate,nstate;
Parameter s0=2 ' B00,
S1=2 ' B01,
S2=2 ' B10;

reg [24:0] cnt = + ' D0;
Reg clk_1hz = 1 ' b0;
[Email protected] (Posedge CLK or Negedge rst_n) begin
if (!rst_n) begin
CNT <= ' D0;
Clk_1hz <= 1 ' b0;
End Else if (cnt>= (cnt_num-1)) begin
CNT <= ' D0;
Clk_1hz <= ~clk_1hz;
End ELSE begin
CNT <= cnt + d1;
End
End
[Email protected] (Posedge clk_1hz or Negedge rst_n)
if (!rst_n) cstate<=s0;
else cstate<=nstate;
[Email protected] (Posedge clk_1hz or Negedge rst_n)
Begin
if (!rst_n) nstate<=s0;
ELSE begin

Case (Cstate)
S0:nstate <= (data) S1:s0;
s1:nstate<= (data) s1:s2;
s2:nstate<= (data) S1:s0;
default:nstate<=s0;
Endcase
End
End
[Email protected] (Posedge clk_1hz or Negedge rst_n)
Begin
if (!rst_n) out<=0;
Else
Case (Nstate)
s0:out<=0;
s1:out<=0;
S2:begin if (data==1) out<=1;
else Out<=0;end
default:out<=0;
Endcase
End
Endmodule

Sequence Detection 101 state machine Implementation