Serial Communication basics and S3C2410 UART Controller

The basic data communication methods can be divided into parallel communication and serial communication: Parallel Communication: it refers to the simultaneous transmission of one piece of data using multiple data transmission lines. It features high transmission speed and is suitable for short-distance communication, but requires a high communication rate. Serial Communication: a transmission line is used to transmit data in a single location in sequence. It is characterized by a simple communication line, which can achieve communication with simple cables and reduce costs. It is suitable for applications with long-distance communication but slow transmission speed. I. asynchronous communication and its Protocols Asynchronous Communication uses one character as the transmission unit. The time interval between two characters in the communication is not fixed. However, the time interval between two adjacent bit codes in the same character is fixed. Communication Protocol (communication rules): rules agreed by both parties. When an asynchronous serial port is used to transmit the information of a character, the following conventions apply to the data format: idle bit, start bit, data bit, parity bit, and stop bit. The timing of asynchronous communication, 5-1. The meanings are as follows: Start position: Sends out a logic "0" signal, indicating the start of the transmission character. Data Location: Followed by the start position. The number of data bits can be 4, 5, 6, 7, 8, and so on. Generally, ASCII code is used. Transmits data starting from the second BIT and locates it by the clock. Parity bit: After the data bit is added, the number of digits of "1" should be an even number (even verification) or an odd number (odd verification) to verify the correctness of the data transfer. Stop bit: Indicates the end of a character. It can be 1-bit, 1.5-bit, or 2-bit high. Idle bit: In the logical "1" status, it indicates there is no data transfer on the current line. Baud Rate: A pointer to the data transfer rate. The number of binary digits transmitted per second. For example, if the data transfer rate is 120 characters/second, and each character is 10 characters, the Transmission baud rate is 10 × 120 = 1200 characters/second = 1200 Potter. Note: asynchronous communication is transmitted by character. After receiving the starting signal, the receiving device can correctly receive the signal as long as it can be synchronized with the sending device during the transmission time of a character. The arrival of the next character's start position also enables synchronous re-calibration (the detection start bit is used to achieve auto-synchronization between the sending and the receiver's clock ). Ii. Data Transmission Method There are three methods based on the data transmission direction. As shown in Figure 5-2.

(1) ticket handling (2) Half Duplex Mode (3) Full Duplex Mode

Figure 5-2 Data Transfer Mode

1. Ticket handling Data is always sent from device A to Device B. 2. Half Duplex Mode Data can be transmitted from device A to Device B, or from Device B to device. At any time, data cannot be transmitted in two directions at the same time, that is, only one device can send data at a time, and the other device can receive the data. However, the communication parties send and receive messages in turn in accordance with certain communication protocols. 3. Full Duplex Mode Both parties are allowed to send and receive messages at the same time. In this case, device A can receive messages at the same time as Device B. The full duplex mode is equivalent to combining two tickets in the opposite direction. Therefore, it requires two data transmission lines. In computer serial communication, half-duplex and full-duplex modes are used. Iii. Signal Transmission Mode 1. baseband transmission mode Directly transmits binary signals without modulation on the transmission line ,. It requires a wide band of transmission lines, and the digital signal transmitted is a Rectangular Wave. The baseband transmission method is only suitable for close-range and low-speed communication. 2. band transmission mode Transmit modulated analog signals During long-distance communication, the sender needs to convert the digital signal to analog signal using a modulation device. Then, the receiver converts the analog signal received by the modem to a digital signal, which is the modulation and demodulation of the signal. The device that implements the modulation and reconciliation task is called a modem ). When band transmission is adopted, both parties connect to a modem to transmit digital signals on analog signals (carriers. Therefore, this transmission method is also called the carrier transmission method. At this time, the communication line can be a telephone exchange network or a dedicated line. There are three common modulation methods: Shows the amplitude modulation, frequency modulation, and phase modulation.

 

Iv. serial interface standards Serial Interface Standard: it refers to the connection Standard between the serial interface circuit of a computer or a terminal (DTE) and a modem (DCE. Standard RS-232C RS-232C is a standard interface, type D socket, connector with 25-core pins or 9-core pins, as shown in 5-5.

Figure 5-5

The serial communication between the microcomputer is implemented according to the interface circuit designed according to the RS-232C standard. If a telephone line is used for communication, the connection between the computer and modem is established according to the RS-232C standard. The connection and Communication Principles are shown in Figure 5-6.

Figure 5-6

RS232 signal Definition The RS-232C Standard specifies that 25 interfaces are online. Only the following 9 signals are frequently used. The pins and functions are as follows: 1. txd (2nd feet): sends data lines and outputs. Send the information to the modem. 2. rxd (3rd feet): receives the data line and inputs it. Receive data to a computer or terminal. 3. (4th feet): Send and output requests. The computer uses this pin to notify the modem to send information. 4. (5th feet): Allow sending, input. A computer can send a message only when the answer is correct. 5. (6th feet): Data device ready (that is, modem ready), input. Indicates that the modem can be used, and the signal is sometimes directly connected to the power supply, which is effective when the device is connected. 6. Cd (8th feet): Carrier Detection (receiver), input. Indicates that the modem has been connected to the telephone line. 7. If the communication line is part of the exchange phone, at least two additional signals are required: 8. RI (22nd feet): indicates the ringing, input. If the modem receives a ringing call signal from the switch station, it sends this signal to inform the computer or terminal. 9. (20th feet): The data terminal is ready for output. After receiving the RI signal, the computer sends the signal to the modem as the answer to control its conversion device and establish a communication link. 10. Gnd (7th feet): Signal Location Logic level RS-232C standard using eia level, provisions: The logical level of "1" is-3v ~ -Between 15 V The "0" logic level is in + 3v ~ + 15 V. Because the EIA level and TTL level are completely different, the corresponding level conversion must be performed. The mcl488 completes the conversion from TTL level to EIA level, and the mcl489 completes the conversion from EIA level to ITL level. In addition, maxcompute can complete the level conversion of TTL-> EIA and EIA-> TTL at the same time. In addition to the RS-232C standard, there are some other general asynchronous serial interface standards, such: Standard RS-423A In order to overcome the disadvantages of RS-232C, increase the transmission rate, increase the communication distance, and take into account the compatibility with RS-232C, the American Association of Electronic Industry proposed RS-423A standards in 1987. The main advantage of this standard is that differential input is adopted at the receiving end. Differential input has a high suppression effect on common-mode interference signals, which improves the communication reliability. RS-423A with-6 V represents the logic "1", with + 6 V represents the logic "0", can be directly connected with the RS-232C. Use RS-423A standards to achieve better communication performance than RS-232C. Figure 5-7 shows the rs423a connection.

Figure 5-7

Standard RS-422A The RS-422A bus uses a balanced output transmitter, a differential input receiver. As shown in Figure 5-8.

Figure 5-8

The voltage between the output signal line of the RS-422A is ± 2 V, and the recognition voltage of the receiver is ± 0. 2 v. Common Mode: ± 25 V. When transmitting signals at high speed, the impedance matching of the communication line should be taken into account. Generally, the terminal resistor is added at the receiving end to absorb the reflected wave. The resistance network should also be balanced, as shown in Figure 5-9.

Figure 5-9 shows the differential output for the RS-422A balanced output

Standard RS-485 RS-485 is suitable for both sides share a pair of lines for communication, also suitable for multiple points to share a pair of lines for bus networking, but the communication can only be half duplex, line 5-10 shows.

Figure 5-10

Typical RS232 to rs422/485 conversion chips include: max481/483/485/487/488/489/490/491, sn75175/176/184, etc, they all work with a single + 5 V power supply (the chip uses a charge pump internally ). For detailed usage, refer to the relevant technical manual.

 

V. UART Controller Built in S3C2410 There are three independent UART controllers in S3C2410, each of which can work in interrupt (Interrupt) mode or DMA (Direct Memory Access) mode, that is to say, the UART Controller can interrupt or DMA requests when the CPU and UART Controller send data. Each UART has a 16-byte FIFO (first-in-first-out register). The maximum baud rate supported is 230.4 kbps. Figure 5-11 shows the structure of the UART Controller in S3C2410.

Figure 5-11

UART operations UART operations are divided into the following parts: data transmission, data receiving, interruption, baud rate, loopback mode, infrared mode, and automatic traffic control mode. Send Materials The format of the sent data frame can be programmed. It contains the start position, 5 ~ 8 data bits, optional parity bits, and 1 ~ 2-bit stop bit. These are all set through the UART control register ulconn. Receiving data The format of received data frames can also be programmed and set like sending. In addition, it can detect overflow errors, parity errors, frame errors, and other errors, and each error can be marked with an error. Automatic traffic control mode Both uart0 and uart1 of S3C2410 can achieve automatic traffic control through their respective nrts and NCTS signals. In the automatic traffic control (AFC) mode, nrts depends on the status of the acceptor, while NCTS controls the operation of sending disconnections. Specifically, UART sends data in the FIFO only when the NCTS is valid (indicating that the receiver's FIFO is ready to receive data. Before the UART receives data, as long as there are at least 2-byte available in the receiving FIFO, nrts will be set to valid. Figure 5-12 shows the connection mode of UART automatic traffic control mode.

Figure 5-12

Interrupt/DMA request generation Each UART of S3C2410 has 7 statuses: overrun) error, parity check error, frame error, disconnection error, ready to receive, idle sending buffer, and idle sending and transferring device. They have corresponding flags in utrstatn/uerstatn. Baud rate generator Each UART Controller has its own baud rate generator to generate the serial clock used to send and receive data. The clock source of the baud rate generator can be the system clock inside the CPU, you can also obtain the clock signal from outside the uclk pin of the CPU, and select the respective clock source through UConn. The method for calculating the baud rate is as follows: When selecting the CPU internal clock: Ubrdivn = (INT) (pclk/(BPS * 16)-1, BPS is the expected baud rate, and pclk is the clock of the CPU's internal peripheral bus (APB. To obtain a more precise baud rate, you can select an external clock introduced by uclk to generate it. Ubrdivn = (INT) (uclk/(BPS * 16)-1 Loopback operation mode The UART of the S3C2410 CPU provides a test mode, that is, the loopback mode. When designing a specific application of the system, in order to determine whether a communication fault is caused by an external data link or a problem with the driver or CPU in the CPU, this requires the loopback mode for testing. In loopback mode, the txd of the Data sender is logically connected to the rxd of the receiver in the UART, and can verify whether the data is sent and received normally. UART control register The following describes the control registers of UART one by one, in order to have a better understanding of the operations and settings of UART. Ulconn (UART line control register) see Figure 5-13

Figure 5-13

Word Length: Data bit length Number of Stop bits: Number of Stop bits Parity mode: parity bit type Infra-red mode: UART/infrared mode (set to "0" when working in UART Mode ") UConn (UART control register) is shown in Figure 5-14 Receive mode: select the receiving mode. If the DMA mode is used, you also need to specify the DMA channel used. Transmit mode: Same as above. Send break signal: Select whether to send the break signal halfway through the transmission of 1 data frame. Loopback mode: Select whether to set UART to the loopback test mode. RX error status interrupt enable: Select whether to enable receiving error interruption when an exception occurs. RX Time Out enable: whether to enable receiving timeout interruption. RX interrupt type: select the receiving interrupt type. Select 0: pulse (pulse type/edge type interrupt. In non-FIFO mode, an interruption occurs when data is in the receiving buffer zone. In FIFO mode, an interruption occurs when data in the FIFO mode reaches a certain trigger level)

Select 1: level (level mode interruption. In non-FIFO mode, data in the receiving buffer zone is interrupted. In FIFO mode, data in the FIFO buffer reaches the trigger level) TX interrupt type: similar to RX interrupt type Clock Selection: select the clock source of the UART baud rate generator.

Figure 5-14

Ufconn (uart fifo conrtol register) see Figure 5-15 FIFO enable: select the FIFO enable. Rx fifo Reset: Select whether to automatically clear the content in the FIFO when the reset receives the FIFO. Tx fifo Reset: determines whether to automatically clear the content in the FIFO when the FIFO is sent. Rx fifo trigger level: select the trigger level for receiving FIFO. Tx fifo trigger level: select the trigger level for sending FIFO.

Figure 5-15

Umconn (UART Modem Control Register) is shown in Figure 5-16 Request to send: In the AFC mode, this bit is automatically set by the UART Controller; otherwise, it must be controlled by the user's software. Auto Flow Control: Select whether to enable automatic flow control (AFC ).

Figure 5-16

Utrstatn (UART Tx/RX Status Register) see Figure 5-17 Receive Buffer Data ready: when the receiving buffer register receives valid data from the UART receiving port, it will automatically set "1 ". Otherwise, "0" indicates that there is no data in the buffer. Transmit buffer empty: When the sending buffer register is empty, "1" is automatically set; otherwise, data in the buffer is waiting for sending. Transmitter empty: when no valid data exists in the sending buffer, "1" is automatically set; otherwise, it indicates that there is still data not sent.

Figure 5-17

Uerstatn (UART error Status Register) see Figure 5-18 Overrun error: "1" indicates an overrun error. Frame Error: 1 ". Frame Error.

Figure 5-18

Ufstatn :( uart fifo Status Register) see Figure 5-19 Rx fifo count: number of bytes currently stored in the receiving FIFO. Tx fifo count: the number of bytes currently stored in the sending FIFO. Rx fifo full: "1" indicates that the receiving FIFO is full. Tx fifo full: "1" indicates that the sending FIFO is full.

Figure 5-19

Umstatn :( uart fifo Status Register) see Figure 5-20 Clear to send: 0 indicates that CTS is invalid; 1 indicates that CTS is valid. Delta CTS: indicates whether the NCTS status has changed since the last time the CPU accessed this bit. If the value is "0", it indicates that the NCTS signal has changed.

Figure 5-20

Utxhn and urxhn are UART data sending and receiving registers, respectively. These two registers store the sent and received data, of course, only one byte of 8-bit data. Note that when an overflow error occurs, the received data must be read. Otherwise, the next overflow error may occur. Ubrdivn :( UART baud rate divisor register) see Figure 5-21

Figure 5-21

The Calculation Method of UART baud rate has been described in detail in the previous content. Summary: The read/write Status Register utrstat and the error Status Register uerstat can reflect the current read/write status and Error Type of the chip. The FIFO Status Register ufstat and modem Status Register umstat can be used to read whether the current FIFO is full and the number of bytes. The latter can be used to read the CTS status of the current modem.