Serial Communication Foundation and S3C2410 UART Controller

The basic way of data communication can be divided into two kinds of parallel communication and serial communication: Parallel communication: Refers to the use of multiple data transmission lines to send a data to each of you simultaneously. It is characterized by fast transmission speed, suitable for short-distance communication, but requires high communication rate applications. Serial communication: Refers to the use of a transmission line to transmit data in a single bit order. Characterized by simple communication lines, the use of simple cable to achieve communication, reduce costs, suitable for long-range communication, but slow transmission of applications. I. Asynchronous communication and its Protocols Asynchronous communication takes one character as the transmission unit, and the time interval between the two characters in the communication is not fixed, whereas the time interval between the two adjacent bit codes in the same character is fixed. Communication Protocol (Communication Regulations): refers to the communication between the two parties agreed to some rules. In the use of asynchronous serial port to transmit a character information, the data format has the following conventions: the provision of idle bit, start bit, data bit, parity bit, stop bit. The timing of the asynchronous communication, as shown in Figure 5-1. The meanings of these members are as follows: starting bit: A logic "0" signal is first emitted to indicate the beginning of the transmission character. Data Level: Immediately after the start bit. The number of data bits can be 4, 5, 6, 7, 8, and so on, constituting a character. ASCII code is usually used. Start from the lowest bit and position by the clock. parity bit: After the data bit is added, the number of "1" should be even (even) or odd (parity), so as to verify the correctness of the data transmission. Stop Bit: It is the end of a character data flag. Can be a 1-bit, 1.5-bit, 2-bit high level. Idle bit: In the logical "1" state, indicates that there is no data transfer on the current line. baud rate: A pointer to the data transfer rate. Represents the number of bits transmitted per second. For example, the data transfer rate is 120 characters per second, and each character is 10 bits, the baud rate transmitted is 10x120=1200 characters per second =1200 baud. Note: Asynchronous communication is transmitted by character, and the receiving device receives the starting signal as long as it is in sync with the sending device during the transmission time of one character. The arrival of the starting bit of the next character also enables synchronous recalibration (relying on the detection of the starting bit to achieve the self-synchronizing of the sending and receiving clocks). Ii. Information Transmission methods There are three ways to vary the direction of data transmission. As shown in Figure 5-2.

(1) Simplex mode (2) Half duplex mode (3) Full duplex mode

Figure 5-2 Data transfer method

1. Simplex mode Data is always sent from device A to device B. 2, half duplex mode Data can be transferred from a device to a B device, or from a B device to a device. Data cannot be transmitted in two directions at any time, i.e. only one device can be sent at a time, and the other device will receive it. But the communication between the two parties in accordance with a certain communication protocol to send and receive in turn. 3, Full duplex mode Allow both sides of the communication to send and receive simultaneously. At this time, a device in the transmission can also receive, B equipment is also the same. The full duplex method is equivalent to combining two opposite single-way, so it requires two data transmission lines. In computer serial communication, the main use is half-duplex and full duplex. Third, signal transmission mode 1, Baseband transmission mode Transmit the non-modulated binary signal directly on the transmission line, as shown in the figure. It requires a wide band of transmission lines, and the transmitted digital signal is a rectangular wave. Baseband transmission is only suitable for short-distance and low-speed communication. 2. Frequency band transmission mode Transmission of modulated analog signals In the long distance communication, the sender will use the modulator to convert the digital signal into an analog signal, and the receiver uses the demodulator to convert the received analog signal into a digital signal, which is the modulation and demodulation of the signal. The device that implements the modulation and demodulation tasks is called a modem. When using the frequency band transmission, each side of the communication is connected to a modem, and the digital signal is sent to the analog signal (carrier) for transmission. Therefore, this transmission is also known as the carrier transmission mode. At this point the communication line can be a telephone exchange network, can also be a dedicated. There are three types of modulation methods commonly used: Amplitude modulation, frequency modulation and phase modulation, respectively, as shown in the figure below.

Four, serial interface standard Serial interface Standard: refers to the connection standard between the serial interface circuit of a computer or terminal (data Terminal equipment DTE) and modem modems, etc. (Data Communication device DCE). RS-232C Standard The rs-232c is a standard interface, D-socket with a 25-pin or 9-pin connector, as shown in Figure 5-5.

Figure 5-5

The serial communication between microcomputers is implemented according to the interface circuit designed by RS-232C standard. If a telephone line is used for communication, the connection between the computer and the modem is based on the RS-232C standard. The principle of connection and communication is shown in Figure 5-6.

Figure 5-6

RS232 Signal Definition The RS-232C standard specifies that the interface has 25 online. Only the following 9 signals are used frequently. The pins and functions are as follows: 1. TXD (2nd leg): Send data line, output. Send data to modem. 2. RXD (3rd leg): Receive data line, input. Receive data to a computer or terminal. 3. (4th leg): Request send, output. The computer notifies the modem via this pin and requests that the data be sent. 4. (5th leg): Allow send, input. The computer can send the data when the answer is given. 5. (6th leg): Data device ready (i.e. modem ready), input. Indicates that the modem can be used, which is sometimes directly connected to the power supply, so that it is valid when the device is connected. 6. CD (8th leg): Carrier detection (receiver line signal detector), input. Indicates that the modem is connected to the telephone line. 7. If the communication line is part of the Exchange phone, then at least two signals are required: 8. RI (22nd foot): ringing indication, input. If the modem receives a ringing call signal from the Exchange station, it sends the signal to notify the computer or terminal. 9. (20th leg): Data terminal ready, output. After the computer receives the RI signal, it sends a signal to the modem as an answer to control its conversion device and establish a communication link. GND (7th leg): Signal ground Logic level The RS-232C standard uses an EIA level, which stipulates: Logic level of "1" between -3v~-15v The logic level of "0" is between +3v~+15v. Since the EIA level is completely different from the TTL level, a corresponding level shift must be performed, MCl488 the conversion of the TTL level to the EIA level, and MCl489 the EIA level to the ITL level. There are also MAX232 that can complete Ttl->eia and Eia->ttl level transitions at the same time. In addition to the RS-232C standard, there are other common asynchronous serial interface standards, such as: RS-423A Standard In order to overcome the shortcomings of rs-232c, increase the transmission rate, increase the communication distance, and consider the compatibility with RS-232C, the American Electronics Industry Association in 1987 put forward the RS-423A standard. The main advantage of this standard is that the differential input is used at the receiving end. The differential input has a high inhibitory effect on the common mode interference signal, which improves the reliability of the communication. RS-423A uses -6v to express logic "1", and uses +6v to represent logic "0", which can be directly connected with rs-232c. Use the RS-423A standard to achieve better communication results than rs-232c. Figure 5-7 is a schematic of the rs423a connection.

Figure 5-7

RS-422A Standard The RS-422A bus uses a balanced output transmitter, a differential input receiver. As shown in Figure 5-8.

Figure 5-8

The voltage between the output signal lines of the rs-422a is ±2v, and the recognition voltage of the receiver is ±0.2v. Co-model Wai ±25v. When transmitting the signal at high speed, the impedance matching of the communication line should be taken into account, and the end resistor is usually added to the receiver to absorb the reflected wave. The resistor network should also be balanced, as shown in Figure 5-9.

Figure 5-9 The rs-422a balanced output differential transmission diagram

RS-485 Standard RS-485 is suitable for both sides to share a pair of lines for communication, but also for multiple points to share a pair of lines for bus mode networking, but the communication can only be half-duplex, the line as shown in Figure 5-10.

Figure 5-10

Typical RS232-to-rs422/485 converters are: max481/483/485/487/488/489/490/491,sn75175/176/184, and so on, they all work with a single power supply (charge pump boost inside the chip). Specific use methods can be found in the relevant technical manuals.

V. s3c2410 built-in UART controller The s3c2410 has 3 independent UART controllers, each of which can operate in interrupt (interrupt) mode or DMA (direct memory access) mode, which means that the UART controller can generate interrupts or DMA requests when the CPU and the UART controller transmit data. And each UART has a 16-byte FIFO (first-in, first-out register) with a maximum baud rate of up to 230.4Kbps Figure 5-11 is a structure diagram of the s3c2410 internal UART controller

Figure 5-11

Operation of the UART The operation of the UART is divided into the following parts: Data transmission, data reception, interrupt generation, baud rate, loopback mode, infrared mode and automatic flow control mode. Send data The format of the sent data frame can be programmed. It contains the starting bit, the 5~8 data bits, the optional parity bit, and the two-to-one stop bit. These are set by the UART's control register Ulconn. Data reception As with sending, the received data frame format can also be programmed. In addition, there are detection of overflow errors, parity errors, frame errors and other error detection, and each error can be placed corresponding error flags. Automatic flow control mode The UART0 and UART1 of s3c2410 can be automatically controlled by their respective nrts and ncts signals. In automatic flow control (AFC) mode The nrts depends on the state of the receiving side, while the NCTS controls the send-off operation. Specifically, the UART sends the data in the FIFO only when NCTS is active (indicating that the receiver's FIFO is ready to receive the data). Before the UART receives the data, the Nrts is set to be valid as long as the receiving FIFO has at least 2-byte free. Figure 5-12 is the way to connect the UART automatic flow control mode

Figure 5-12

Interrupt/DMA Request Generation Each UART in the s3c2410 has 7 states, namely: overflow overwrite (overrun) error, parity error, frame error, wire break error, receive ready, send buffer idle, send shifter idle. They have a corresponding flag bit in the UART status register Utrstatn/uerstatn. Baud Rate Generator Each UART controller has its own baud rate generator to generate the sequence clocks used to send and receive data, the clock source of the baud rate generator can be the system clock inside the CPU, and the clock signal can be obtained externally from the UCLK pin of the CPU, and the individual clock source can be selected by UConn. The specific calculation method for baud rate generation is as follows: When selecting the CPU internal clock: ubrdivn= (int) (pclk/(bps*16)) -1,bps is the desired baud rate value, and PCLK is the working clock of the internal peripheral bus (APB) of the CPU. When more accurate baud rates are needed, the external clock introduced by UCLK can be chosen to generate. ubrdivn= (int) (uclk/(BPS*16))-1 Loopback operation mode The UART of the S3C2410 CPU provides a test mode, which is the loopback mode described here. In the design of the specific application of the system, in order to determine the communication failure is due to external data link problems, or CPU driver or CPU itself, this need to use the loopback mode to test. In the loopback mode, the data sending end TXD in the UART is logically connected to the receiving end rxd, and can be used to verify that the data is sent and received properly. UART Control Register Each control register for the UART is explained below, with a view to further understanding the operation and setup of the UART. Ulconn (UART line Control Register) See figure 5-13

Figure 5-13

Word Length: Data bit length Number of Stop bit: stop bits Parity Mode: Parity bit type Infra-red mode:uart/IR mode selection (set to "0" when working in UART mode) UConn (UART Control Register) See figure 5-14 Receive mode: Select the receive pattern. If you are using DMA mode, you also need to specify the DMA channel that is used. Transmit Mode: Ibid. Send Break Signal: Choose whether to send a break signal halfway through the 1-frame data. Loopback mode: Select whether to place the UART in Loopback test mode. Rx error Status Interrupt enable: Select whether to enable receive error interrupts when a receive exception occurs. Rx Time Out enable: Enable to receive timeout interrupts. Rx Interrupt Type: Select the receive interrupt types. Select 0:pulse (Pulse/edge type interrupt. In the non-FIFO mode, an interrupt is generated once the receiving buffer has data, and in FIFO mode, an interrupt occurs once the data in the FIFO reaches a certain trigger level.

Select 1:level (Level mode interrupt.) In the non-FIFO mode, interrupts are generated whenever there is data in the receive buffer, and in FIFO mode, as long as the data in the FIFO reaches the trigger level, the interrupt is generated. Tx Interrupt type: Similar to RX Interrupt type Clock Selection: Select the clocking source of the UART baud rate generator.

Figure 5-14

Ufconn (UART FIFO conrtol Register) See figure 5-15 FIFO Enable:fifo enable selection. Rx FIFO Reset: Select whether to automatically purge content in the FIFO when the receive FIFO is reset. Tx FIFO Reset: Select whether to automatically purge the contents of the FIFO when the Send FIFO is reset. Rx FIFO Trigger level: Select the trigger levels for the receive FIFO. Tx FIFO Trigger level: Select the trigger levels for the send FIFO.

Figure 5-15

Umconn (UART Modem Control Register) See figure 5-16 Request to Send: If in AFC mode, the bit will be set automatically by the UART controller, otherwise it must be controlled by the user's software. Auto flow control: Select whether to enable automatic flow control (AFC).

Figure 5-16

Utrstatn (UART tx/rx Status Register) See figure 5-17 Receive buffer data ready: "1" is automatically placed when the receive buffer register receives valid data from the UART receive port. Conversely, "0" means that there is no data in the buffer. Transmit buffer empty: When the send buffer register is empty, the "1" is automatically set, whereas the buffer has data waiting to be sent. Transmitter empty: When there is no valid data in the transmit buffer, the "1" is automatically set, and the reverse indicates that the data is still not sent.

Figure 5-17

Uerstatn (UART Error Status Register) See figure 5-18 Overrun error: "1" indicates a overrun error occurred. Frame Error: "1". Indicates a frame (frame) error occurred.

Figure 5-18

Ufstatn: (UART FIFO Status Register) See figure 5-19 Rx FIFO Count: The number of bytes currently held in the receive FIFO. Tx FIFO Count: The number of bytes currently stored in the Send FIFO. Rx FIFO full: "1" indicates that the receive FIFO is fully filled. Tx FIFO full: "1" indicates that the send FIFO is fully filled.

Figure 5-19

Umstatn: (UART FIFO Status Register) See figure 5-20 Clear to Send: The CTS is invalid for "0", and "1" indicates that the CTS is valid. Delta CTS: Indicates whether the state of the NCTS has changed since the last time the CPU accessed the bit. The "0" indicates that the NCTS signal has changed since it was never changed.

Figure 5-20

Utxhn and Urxhn are UART transmit and receive data registers respectively These two registers hold the data sent and received, of course, only one byte 8 bits of data. It is important to note that when an overflow error occurs, the received data must be read out, or the next overflow error will be raised UBRDIVN: (UART Baud rate Divisor Register) See figure 5-21

Figure 5-21

The method of calculating UART baud rate is described in detail in the previous content, and no superfluous explanation is made here. Summary : read-write status register utrstat and error status register Uerstat can reflect the current read and write status of the chip and the type of error. FIFO Status register Ufstat and modem State Register Umstat, through the former can read out the current FIFO is full and the number of bytes, through the latter can read the current modem CTS state.