Serial RapidIO: High-performance embedded interconnect technology--"repost"

Serial RapidIO: High-performance embedded interconnect technology Author: Texas Instrument technology Application Engineer Feng Hualiang/Brighton feng/[email protected] Summary Designed for high-performance embedded system chips and inter-board interconnect, the serial RapidIO is the best choice for embedded systems interconnection over the next more than 10 years. This paper compares the advantages of RapidIO and traditional interconnection technology, introduces RapidIO protocol architecture, packet format, interconnect topology, and serial RapidIO Physical layer specification. This paper introduces the application of serial RapidIO in wireless infrastructure. Comparison of RapidIO and traditional embedding interconnection methods With the continuous development of high-performance embedded systems, inter-chip and inter-board interconnection to the bandwidth, cost, flexibility and reliability of the more and more high, traditional interconnection methods, such as processor bus, PCI bus and Ethernet, are difficult to meet the new requirements. The processor bus is mainly used as external memory interface, such as Texas Instruments (TI) C6000 series DSP external memory interface, can support external synchronization SDRAM, Sbsram and FIFO, but also support asynchronous SRAM, Flash and so on. The external memory interface can also be used for interconnection with an in-board FPGA or ASIC chip, in which case the FPGA or ASIC simulates a DSP-supported memory interface, and the DSP accesses the FPGA or ASIC as memory. This type of synchronization interface bandwidth up to 10Gbps, such as the Texas Instrument tms320c6455 DSP DDR2 Interface Maximum bandwidth of 17.066gbps,sbsram interface maximum bandwidth of 8.533Gbps. However, there are some limitations to this interface: The interface pin is many, the hardware design is difficult. A common DDR2 interface has 70~80 pins; Can only be used for in-board interconnection, can not be used for inter-board interconnection; The DSP is not a peer peering, it is always the primary device, and the other devices can only be made from the device. PCI is widely used in computer-based device interconnection technology. Traditional PCI technology also samples parallel bus mode similar to the above memory interface, such as tms320c6455 DSP PCI interface, there is a 32bits data bus, the highest clock speed of 66MHz, a total of 42 pins. The latest serial PCI Express technology uses a physical layer transfer technology similar to the serial RapidIO (SRIO, Serial RapidIO), allowing bandwidth to reach around 10Gbps. But because its main application is still a computer, and in order to be compatible with the traditional PCI technology, it has certain limitation in the application of embedded device, such as the point-to-point peering communication is not supported. As we all know, Ethernet is the most widely used LAN interconnect technology, it is also extended to embedded device interconnection, but its limitations are also obvious: Hardware error correction is not supported and the software protocol stack is expensive. The packaging efficiency is low, and the effective transmission bandwidth decreases. Only the message transfer mode is supported, and direct memory access to the peer device (DMA, directly memory access) is not supported. In response to the requirements of embedded systems and the limitations of traditional interconnection methods, the RapidIO standard is formulated as follows: Designed for high-speed interconnect applications in embedded system machines. Simplify the protocol and flow control mechanism, limit the complexity of software, make the error-correcting retransmission mechanism and even the whole protocol stack easy to implement with hardware. Improve packaging efficiency and reduce transmission delay. Reduce the cost by reducing the pin. simplifies the implementation of the switching chip and avoids packet type resolution in the switching chip. Layered protocol architecture, supports multiple transfer modes, supports multiple physical layer technologies, and is flexible and easy to scale. Figure 1 shows the application of RapidIO interconnect in embedded systems. Figure 1 Application of RapidIO in embedded system Table 1 summarizes the comparison of the three bandwidth can reach 10Gbps Interconnect technology: Ethernet, PCI Express and Serial RapidIO, from which we can see that the serial RapidIO is the most suitable for high-performance embedded system interconnection technology. Table 1 Comparison of 10G level interconnection technologies The software realizes the Ethernet of TCP/IP protocol stack 4x PCI Express 4x SRIO Note Software overhead High In Low SRIO protocol stack is simple, generally hardware implementation, software overhead is very small Hardware error correction retransmission Not supported Support Support Transfer mode News Dma DMA, message Topological structure Any PCI Tree Any Srio supports direct point-to-point or various topologies implemented by switching devices Direct point-to-point peering interconnection Support Not supported Support Srio interconnection between the two parties can initiate the transmission. Transmission distance Long In In Srio for embedded devices internal interconnect, transmission distance is generally less than 1 meters Maximum payload length of the packet 1500 bytes 4096 bytes 256 bytes Embedded communication system requires high real-time, Srio packet transmission can reduce transmission delay Packaging efficiency (in the case of transmitting 256 bytes of data) 79% (TCP packet) 82% 92~94% Packing efficiency is the ratio of payload length to total package length. Srio supports a variety of efficient package formats. Serial RapidIO Protocol Founded in 2000, the RapidIO Industry Association aims to develop reliable, high-performance, packet-switched interconnect technologies for embedded systems. The brief development history of the RapidIO Agreement is: Early 2001, the initial standards were released June 2002, 1.2 release of standard June 2005, 1.3 release of annotations Serial RapidIO is the RapidIO standard of the physical layer using serial differential analog signal transmission. The SRIO 1.x standard supports a signal speed of 1.25GHz, 2.5GHz, 3.125GHz, and the RapidIO 2.0 standard being developed will support 5GHz, 6.25GHz. At present, almost all of the embedded system chip and equipment suppliers have joined the RapidIO Industry Association. Texas Instruments (TI) joined the organization in 2001 and became a member of the leadership Committee in 2003. At the end of 2005, Texas Instruments (TI) launched the first integrated Srio (Serial RapidIO) DSP, and later introduced a total of 5 support Srio DSP, which makes the application of RapidIO fully launched. RAPIDIO protocol structure and package format To meet the requirements of flexibility and scalability, the RapidIO protocol is divided into three tiers: the logic layer, the transport layer, and the physical layer. Figure 2 illustrates the hierarchical structure of the RapidIO protocol. Figure 2 RapidIO Protocol hierarchy The logic layer defines the operation protocol, the Transport layer defines the packet switching, routing and addressing mechanisms, and the physical layer defines the electrical characteristics, link control, and error-correcting retransmission. Like Ethernet, RapidIO is also an interconnect technology based on packet switching. As shown in 3, the RapidIO package consists of Baotou, optional load data, and 16bits CRC checksum. The length of the Baotou may be more than 10 to more than 20 bytes, depending on the package type. The load data per packet is not more than 256 bytes in length, which facilitates the reduction of transmission delay and simplifies hardware implementation. Figure 3 RapidIO Package format The package format definition takes into account the efficiency of the package and the simplicity of the package/unpack. The RapidIO switching device only needs to parse before and after 16bits, as well as the source/target device ID, which simplifies the implementation of the switching device. Logic Layer Protocol The logical layer defines the operation protocol and the corresponding package format. RapidIO supports a logical layer of business primarily: direct IO/DMA (directly io/direct Memory Access) and messaging (message passing). The direct IO/DMA mode is the simplest and most practical transmission method, provided that the primary device knows the memory map of the accessed side. In this mode, the master device can read and write directly from the device's memory. The function of direct IO/DMA on the accessed side is often implemented entirely by hardware, so the device being accessed will not have any software burden. Functionally speaking, this feature is similar to the traditional host interface (HPI, host Port Interface) of the Texas Instruments DSP. However, compared with the HPI port, SRIO (Serial RapidIO) has a large bandwidth, fewer pins and more flexible transmission modes. For upper-layer applications, initiating direct IO/DMA transmission mainly requires the following parameters: The target device ID, data length, the address of the data in the memory of the target device. The direct IO/DMA mode can be further divided into the following transmission formats: Nwrite: Write operation, does not require receive-side response. Nwrite_r: Nwrite with response (Nwrite with Response), which requires a receive-side response. Swrite: Stream Write, the data length must be an integer multiple of 8 bytes and does not require a receive-side response. Nread: Read operation. Swrite is the most efficient transmission format, with a lower efficiency for write or read operations with response, and generally only half the efficiency of a non-responsive transmission. Messaging (message passing) mode is similar to the way Ethernet is transmitted, and it does not require the primary device to know the memory condition of the device being accessed. The location of the data in the device being accessed is determined by the mailbox number (similar to the port number in the Ethernet protocol). The process of saving data to the corresponding buffer from the mailbox number of the received package, which is often not fully hardware-based, requires software assistance, which can lead to some software burdens. For upper-level applications, initiating message delivery mainly requires the following parameters: Target device ID, data length, mailbox number. Table 2 compares the direct IO/DMA and message delivery patterns. Table 2 Comparison of direct IO/DMA and message passing Direct IO/DMA Message delivery The host has direct access to slave memory? OK No Does the host need to know the slave memory map? Need Don't need Data addressing methods Memory address Mailbox number Supported ways to access data Read/write Write Slave software Burden No Yes Transport Layer Protocol RapidIO is an interconnect technology based on packet switching, and the transport layer defines the routing and addressing mechanisms for packet switching. The RapidIO network consists of two devices, an end point and a switching device (switch). The terminal device is the source or destination of the packet, and different terminal devices are differentiated by the device ID. The RapidIO supports a 8 bits or a BITS device ID, so a rapidio network can accommodate up to 256 or 65,536 terminal devices. Similar to Ethernet, RapidIO also supports broadcast or multicast, and each terminal device can be configured with a broadcast or multicast ID in addition to its unique device ID. The switching device forwards the packet according to the device ID of the packet, and the switching device itself has no device ID. The interconnect topology of the RapidIO is very flexible, and the two terminal devices can be directly interconnected, in addition to switching devices. Take Texas Instruments (TI) tms320c6455 DSP as an example, it has 4 3.125G Srio port, it can support the topology shown in 4. Figure 4 RapidIO supports a flexible and diverse topology Physical Layer Protocol The RapidIO 1.x protocol defines the following two physical layer interface standards: 8/16 Parallel LVDS Protocol 1x/4x Serial Protocol (SRIO) Parallel RapidIO because of the signal line more (40~76) difficult to obtain a wide range of applications, and 1x/4x serial RapidIO only 4 or 16 signal lines, gradually become mainstream, so this article only introduce serial rapidio. The serial RapidIO is based on the SerDes (Serialize deserialize) technology, which is now widely used in Backplane interconnect, which uses differential AC-coupled signals. The differential AC-coupled signal has the advantages of strong anti-jamming, high speed and long transmission distance. The quality of the differential AC-coupled signal is not measured by conventional timing parameters, but by eye-view, the better the signal quality, the more open the eye in the eye. Figure 5 is an eye diagram of a typical serial rapidio signal. Figure 5 Serial RapidIO signal eye diagram The strength of the differential signal is represented by the voltage difference of a pair of signal lines, and the serial RapidIO protocol specifies that the peak-to-peak range of the signal is 200mv-2000mv. The larger the signal amplitude, the farther the transmission distance is, the RapidIO protocol defines two transmission metrics according to the signal transmission distance: Short Run, <=50 cm, mainly for in-board interconnection, recommended peak-to-peak signal for the sending end is 500MV-1000MV Long distance transmission (long Run), >50 cm, mainly used for board or Backplane interconnection, recommended peak-to-peak signal of the transmitter is 800MV-1600MV In order to support full duplex transmission, the serial RapidIO transceiver signal is independent, so each serial RapidIO port consists of 4 signal lines. The standard 1x/4x serial RapidIO interface supports four ports and a total of 16 signal lines. These four ports can be used as separate interfaces to transmit different data, or they can be combined together as an interface to improve throughput on a single interface. The Texas Instruments tms320c6455 DSP is integrated with the standard 1x/4x serial RapidIO interface, shown in 6. Figure 6 Texas Instruments tms320c6455 DSP 1x/4x serial RapidIO interface block diagram At the time of sending, the logical layer and the transport layer will be sent to the FIFO of the physical layer after the good package is CRC encoded, the "8B/10B encoding" module encodes every 8bit data into 10bits data, and the "and/or string conversion" module converts 10bits parallel data into serial bits, The transmit module converts the digital bit into a differential AC-coupled signal that is sent out on the signal line. The main functions of the 8B/10 coding here are: Ensure that the signal has enough jumps to allow the receiver to recover the clock. The serial RapidIO does not have a dedicated clock signal line, and the receiving end relies on the data signal's jump to restore the clock. Therefore, 8bits data (such as full 0 or full 1) with less signal jumps must be encoded into 10bits data with a certain jump. In addition, the number of 0 and 1 in the overall data is balanced to eliminate the DC component and ensure the AC coupling characteristic. 8B/10 encoding expands the symbol space to host in-band control symbols. 10bits can represent 1024 symbols, 256 of which represent valid 8bits data, and dozens of of the remaining symbols are used as control symbols. Control symbols can be used as packet separators, response flags, or for link initialization, link control and other functions; 8B/10 coding can realize certain error-checking function. 1024 symbols, in addition to 256 valid data symbols and dozens of control symbols, the other symbols are illegal, the receiver received an illegal symbol indicates a link transmission error. The receiving process is just the opposite, first the receiver needs to recover the clock according to the data signal jump, use this clock to sample the serial signal, convert the serial signal to 10bits parallel signal, and then according to 8B/10B encoding rules decoding to get 8bits data, and finally do CRC check and send the upper layer processing. When the data is received correctly, the receiving end sends an ACK response packet to the sending side, and if the data is incorrect (CRC error or illegal 10bits symbol), the NACK packet is sent and the sender is required to retransmit it. This retransmission function is done by the physical layer, and the physical layer functions are often implemented by hardware, so software intervention is not required. There are three types of signal rates supported by serial RapidIO: 1.25ghz,2.5ghz,3.125ghz. However, due to the 8B/10B encoding, the valid data rates are: 1Gbps, 2Gbps, 2.5Gbps, respectively. 4 x 1x ports or one 4x port supports a maximum rate of 10Gbps. Application of serial RapidIO in wireless infrastructure Wireless infrastructure such as base station, media gateway, etc., is a typical high-performance embedded communication system, they have very high requirements for interconnection bandwidth, delay, complexity, flexibility and reliability. Serial RapidIO is the best choice to meet these requirements. As an example of a wireless base station, a typical block diagram of baseband processing for a wireless base station is shown in 7 before the Srio occurs. Figure 7 Traditional wireless base station baseband processing block diagram In a traditional base station, the interconnect between the DSP and ASIC or FPGA is generally used external memory interface EMIF (External memory Interface), between DSP or DSP and the host is generally used HPI (host Port Interface) or PCI interconnect. Their main disadvantage is: The bandwidth is small, the signal line is many, the master-slave mode interface, does not support peer transmission. In addition, the DSP can not directly carry out backplane transmission. Using Srio (Serial RapidIO) can effectively solve these problems and greatly improve the interconnection performance of wireless base stations. Figure 8 shows a wireless base station baseband interconnect block diagram. Here, the Srio enables the interconnection of most devices, and even supports direct backplane transmission by DSP. Figure 8 Srio improve wireless base station interconnect performance The flexibility of baseband processing can be further improved through the Srio switching device interconnect, and Figure 9 shows a block diagram of a baseband Srio interchange interconnect. This interconnection facilitates the implementation of the advanced baseband processing resource pool architecture, and data can be sent to any processor connected via the Srio switch, thus achieving load balancing of each processor and making more efficient use of the system's overall processing power. Figure 9 Srio switching provides greater flexibility for baseband processing of wireless base stations In summary, the serial RapidIO is the best interconnection technology for embedded system, especially wireless infrastructure. Up to 10Gbps of bandwidth, low latency and low software complexity meet the demanding performance demands of fast-growing communication technologies; The serial differential analog signal technology satisfies the system's limit to the number of pins and the demand for the transmission of the backplane; flexible peer-to-peer interconnection, exchange interconnect, and optional 1.25g/2.5g/ 3.125G three speeds to meet the needs of many different applications. With the development of serial RapidIO technology and the support of more and more vendors, serial RapidIO technology will become the mainstream technology of high performance embedded interconnection.

Serial RapidIO: High-performance embedded interconnect technology--"repost"