[Serialization] An example of FPGA-based FPGA Series-Series Signal Generator

[Serialization] FPGA OpenGL series instances

Sequence Signal Generator Based on OpenGL

I. Principles

In digital circuits, serial signals are a series of periodic binary signals cyclically generated by synchronous pulses. the logic device that can generate such a signal is called a sequence signal generator. according to the structure, it can be divided into two types: Feedback Shift Type and counting type.
A shift-type serial signal generator consists of a shift register and a combined circuit. The output of the combined circuit serves as the serial input of the shift register.
The counting sequence signal generator can generate multiple sets of sequence signals, which are not functions of the shift sequence generator. The counting sequence signal generator consists of a counter and a combination circuit.
The purpose of this experiment is to design a sequence signal generator. Design a counting series signal generator circuit that generates sequences of 11100100, 11100100, and.

II. Implementation

In the design file, enterCode

Anti-shake Module

 1      /* ********* ***************************  */  
  2   
  3   'Timescale  1  NS  /     1  PS
  4   Module qu_dou (CLK, RST, A, B );
  5  
  6   Input CLK;
  7   Wire CLK;
  8   Input RST;
  9   Input;
  10   Wire;
  11   
  12   Output B;
  13  Reg B;
  14   
  15   Reg [  31  :  0  ] CNT;
  16   Reg clkout;
  17   Always @ (posedge CLK or negedge RST)
  18   Begin
  19    If  (RST  =     1  '  B0)  
  20     CNT  <=     0  ;
  21    Else  Begin  If  (  =  1  '  B1) begin  
  22       If  (CNT  > =     32  ' D3000000)  
  23     B  <=     1  ;
  24     Else   
  25   CNT  <=  CNT +     1  '  B1;  
  26     
  27   End
  28     Else  Begin B  <=    1  '  B0;  
  29     CNT  <=     0  ;
  30   End
  31   End
  32   End
 33   
  34   
  35   Endmodule 

Function implementation

 1   'Timescale  1  NS  /     1  PS
  2   
  3  Module xlgen (Q, CLK, res, RST, sysclk );
  4   
  5   Input CLK;
  6   Wire CLK;
  7   Input res;
  8   Wire res;
  9   Input sysclk;
  10   Input RST;
  11  
  12   Output Q;
  13   Reg Q;
  14   Reg [  7  :  0  ] Q_r;
  15   
  16     /*  ******************** **************** */  
  17   Wire clk_r;
  18   Qu_dou (
  19   . CLK (sysclk ),
  20   . RST (RST ),
  21   . A (CLK ),
  22   . B (clk_r ));
  23   
 24     //  **************************************** ****************************  
  25     
  26   Always @ (posedge clk_r or posedge res)
  27   Begin
  28   
  29    If  (Res  =  1  ) Begin
  30   Q  <=     1  '  B0;  
  31     Q_r  <=    8  '  B11100100;  
  32     End
  33     Else  
  34   Begin
  35   Q  <=  Q_r [ 7  ];
  36   Q_r  <=  Q_r  <  1  ;
  37   Q_r [  0  ]  <=  Q;
  38   End
 39   End
  40   
  41   Endmodule