[Serialization] An example of FPGA-based series-sequential Pulse Generator

[Serialization] FPGA OpenGL series instances

Sequence Pulse Generator Based on OpenGL

I. Principles

In a digital circuit, a circuit that can output pulse waveforms in turn in a certain order of time is called a sequential pulse generator. In digital systems, it is often used to control certain devices to perform operations or operations in the order specified in advance.
A sequence pulse generator is also called a pulse distributor or a beat pulse generator. It generally consists of a counter (including a shift register counter) and a decoder. As a time reference, the counting pulse is sent from the input end of the counter. the decoder translates the counter status into the sequence pulse on the output end so that the status on the output end takes turns to 1 in a certain time and order, or the rotation value is 0. The sequence pulse generator is divided into counter-type sequence pulse generator and shift-type sequence pulse generator.
The counter-type ordered pulse generator is generally composed of binary counters and decoders counting in the natural order. The shift sequence pulse generator consists of a shift register counter and a decoding circuit. The output of the ring counter is a sequence pulse, so the sequence pulse generator can be directly used without decoding circuit.

II. Implementation

In the design file, enterCode

 1      /* ********* ***************************  */  
  2   
  3   'Timescale  1  NS  /     1  PS
  4   Module qu_dou (CLK, RST, A, B );
  5  
  6   Input CLK;
  7   Wire CLK;
  8   Input RST;
  9   Input;
  10   Wire;
  11   
  12   Output B;
  13  Reg B;
  14   
  15   Reg [  31  :  0  ] CNT;
  16   Reg clkout;
  17   Always @ (posedge CLK or negedge RST)
  18   Begin
  19    If  (RST  =     1  '  B0)  
  20     CNT  <=     0  ;
  21    Else  Begin  If  (  =  1  '  B1) begin  
  22       If  (CNT  > =     32  ' D3000000)  
  23     B  <=     1  ;
  24     Else   
  25   CNT  <=  CNT +     1  '  B1;  
  26     
  27   End
  28     Else  Begin B  <=    1  '  B0;  
  29     CNT  <=     0  ;
  30   End
  31   End
  32   End
 33   
  34   
  35   Endmodule 

Function implementation

 1   'Timescale  1  NS  /     1  PS
  2   
  3  Module pulsegen (Q, CLR, CLK, sysclk, RST );
  4   
  5   Input CLR;
  6   Wire CLR;
  7   Input CLK;
  8   Wire CLK;
  9   Input sysclk;
  10   Wire sysclk;
  11  Input RST;
  12   Wire RST;
  13   
  14   Output [  7  :  0  ] Q;
  15   Wire [  7  :  0  ] Q;
 16   Reg [  7  :  0  ] Temp;
  17   Reg X;
  18   
  19     /*  ******************** ****************  */  
  20  Wire clk_r;
  21   Qu_dou (
  22   . CLK (sysclk ),
  23   . RST (RST ),
  24   . A (CLK ),
  25   . B (clk_r ));
  26   
  27     // **************************************** ****************************  
  28     Assign Q  =  Temp;
  29   Always @ (posedge clk_r or posedge CLR)
  30   Begin
  31     If  (CLR  = 1  )
  32   Begin
  33   Temp  <=     8  '  B00000001;  
  34     X  =    0  ;
  35   End
  36     Else  
  37   Begin
  38   X  <=  Temp [  7  ];
  39  Temp  <=  Temp  <  1  ;
  40   Temp [  0  ]  <=  X;
  41   End
  42   End
  43  Endmodule