[Serialization] FPGA-based SSD series instance-3-8 Decoder

[Serialization] FPGA OpenGL series instances

3-8 Decoder Based on OpenGL

I. Principle:

Decoding is the inverse process of encoding. Its function is to identify binary codes with specific meanings and convert them into control signals. A logic circuit with decoding function becomes a decoder.
The decoder can be divided into two types:CodeConvert to one of the valid signals. This decoder can be called a unique address decoder. It is often used for decoding the address of a memory unit in a computer. It replaces each address code with a valid signal and selects the corresponding unit. The other is to convert one type of code into another type of code, which is also called Code Converter.

Figure 1.1 3-8 decoder truth table

II. Implementation

Enter the OpenGL code in the design file.

 1   'Timescale  1  NS /     1  PS
  2   
  3   Module decoder3_8 (G1, Y, G2, A, G3 );
  4   
  5   Input G1;
  6   Wire G1;
  7   Input G2;
  8  Wire G2;
  9   Input [  2  :  0  ];
  10   Wire [  2  :  0  ];
  11   Input G3;
  12   Wire G3;
 13   
  14   Output [  7  :  0  ] Y;
  15   Reg [  7  :  0  ] Y;
  16   Reg S;
  17   
 18   Always @ (A, G1, G2, G3)
  19   Begin
  20   S  <=  G2  |  G3;
  21     If  (G1  =     0 )
  22   Y  <=     8  '  B1111_1111;  
  23       Else     If  (S)
  24  Y  <=     8  '  B1111_1111;  
  25       Else  
  26     Case  ()
  27    3  '  B000: y <= 8  '  B1111_1110;
  28     3  '  B001: y <= 8  '  B1111_1101;
  29     3  ' B010: y <= 8  '  B1111_1011;
  30     3  '  B011: y <= 8  '  B1111_0111;
  31     3  '  B100: y <= 8  ' B1110_1111;
  32     3  '  B101: y <= 8  '  B1101161111;
  33     3  '  B110: y <= 8  '  B1011_1111;
  34    3  '  B111: y <= 8  '  B0111161111;
  35   Endcase
  36   End
  37   
  38   Endmodule