[Serialization] [FPGA black gold Development Board] Those things of OpenGL-low-level modeling resources (6)

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• Experiment 3 Configuration

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Low-level modeling involves resource allocation. The purpose is to use "graphics" to improve the solution of modeling.

The diagram is the most basic modeling block for low-level modeling. It is estimated that you have been familiar with it in Experiment 1 and Experiment 2. The function module (low-level function module) is a horizontal rectangle, while the control module (low-level control module) is a rectangle. The combination module can be any shape (random square ). Note that both the function module and control module contain "module name" and ". V File Name". On the contrary, the combination module only contains ". V file name ".

Each "low-level modeling resource" task is named like itself. Examples of functional modules include "flash_module.v", examples of control modules include "run_module.v", and "mix_module.v" is a combination module.

A complete modeling is based on the basic resources on the graph, "combined and combined ". Of course, there is a problem with low-level modeling, that is, there is a large amount of modeling, but this problem is wise, because different people have different combinations of habits. In addition, a mandatory criterion for low-level modeling is that "one function module (Control Module) has only one function"

. Why is this criterion so important?

Because low-level modeling uses "graphs" to express a complete module. The relationship between modules is expressed by "signals.

Assume an example: a boss commands an employee. Boss (control module), and employee (function module ). If you think about it from another perspective, "the boss sends the code" and "the employee works ". "Link" indicates that they are "subject relationships ".

Or another example: an old employee sends a number to a new employee. In reality, old employees come to work (functional modules), while new users also come to work (functional modules ). However, old employees sometimes need support from new users. As shown in the figure above, we can infer from the "connection" that the results will be "visible", that is, "a novice relationship"

The above two examples show that I strongly advocate that "one function module (Control Module) has only one function ". Because of this, the solution will be greatly improved, and the modeling is easier and more diversified than the first time.

Two examples alone cannot illustrate the benefits of "low-level modeling". We will understand it from the design through a simple experiment.

Experiment 3: One of the deshake modules

The figure shows a simple key shake module. The design method is mainly composed of the "level check module" and "10 ms delay module.

The design logic is as follows:

1) Once the key resource is detected to be pressed (high-level to low-level changes), the "level check module" will increase

H2l_sig level, and then pull down.

2) the "10 ms latency module" detects the high level of h2l_sig, and then uses 10 ms to filter h2l_sig and pull the height.

Output

3) when the "level detection module" is released, the l2h_sig level will be increased and then lowered.

4) The "10 ms latency module" checks l2h_sig to filter h2l_sig with 10 ms, and then pulls down the output.

Experiment three source code: Tutorial 3:

Detect_module.v is a level detection function module. The 14 rows define the constants of 18th us, while ~ 30 rows are used to delay us. Because the level detection module is very sensitive, the level is easy to be unstable at the moment of reset. The Isen = 1 Register indicates that the latency of us has been completed (28 rows ).

34th ~ Line 37 declares four registers. H2l_f1, h2l_f2, is designed for the detection level from high to low. In contrast, l2h_f1 and l2h_f2 are used to increase the detection level from low to high. In 41 ~ Row 46, initialized for each register, because h2l_fx is to detect the level from high to low, so the initialization logic 1. L2h_fx is used to detect the level from low to high. The initial value is set to logical 0.

// Initialization

H2l_f1 <= 1 'b1;

H2l_f2 <= 1 'b1;

// Operations at each time

H2l_f1 <= pin_in;

H2l_f2 <= h2l_f1;

// Boolean operation output for each time

Pin_out = h2l_f2 &! H2l_f1

AboveCodeIs used to detect the level from high to low. The initial values of h2l_f1 and h2l_f2 are logical 1. Assuming that the first time pin_in is low, h2l_f1 will be assigned a value of logic 0, while h2l_f1 is assigned a value of time on h2l_f1 (that is, the initial value of h2l_f1 ).

We know that at the first time, h2l_f1 is logical 0, and h2l_f2 is logical 1. Because of the inverse operation on h2l_f1, the output of this expression is logical 1.

Assuming that pin_in remains low for the second time, h2l_f1 will also be assigned a value of logic 0, while h2l_f2 is assigned a value of time on h2l_f1, that is, logic 0 (the value of the first time ). After a Boolean expression operation, in the second time, h2l_f1 is logical 0, while h2l_f2 is logical 0, so the output result is logical 0.

time	h2l_f1	h2l_f2	pin_out = h2l_f2 (! H2l_f1)
initial	1	1	0
t1	0	1	1
t2	0	0	0

48th ~ In row 53, the above operations are performed. The idea is basically the same whether the detection level changes from high to low or from low to high. The last 58 ~ Row 59 is a Boolean expression about "level detection. However, the difference is that the output of pin_out occurs after 100us, because 100us is limited by the Isen register (as mentioned earlier ). In other words, level detection is effective after 100us latency.

Delay_module.v is a 10 ms delay function module. The module is written in the form of "Imitation sequential operations" (chapter 4 ). 16th ~ The 42 lines are written as "latency", 18th ~ 28 rows are 1 ms timers, while 32nd ~ 40 rows are counters. Both the timer and counter are enabled by the iscount mark register.

44th ~ The 71 rows are "sequential operations" (chapter 4), and the 46th rows of I registers are used to control the execution steps. At the beginning, I will enter different steps according to "h2l_sig" or "l2h_sig" (58 ~ 60 rows ). From 62 ~ 64, or 66 ~ The 68 rows are all operations with a latency of 10 ms. in different places, only the value of the rpin_out register is assigned (63 rows and 67 rows ).

Let's take a brief look at the location ~ 71 lines of design ideas:

1) if the h2l_sig signal has a response, go to step 1,

2) After step 1 is entered, because the if condition is not met, iscount enables. Timer. The counter starts execution.

3) after 10 ms, the iscount is not enabled. The timer and counter are stopped. Rpin_out is logical 1

. Return to step 0.

Or:

1) if the l2h_sig signal has a response, go to step 2,

2) After step 2 is entered, because the if condition is not met, iscount enables. Timer. The counter starts execution.

3) after 10 ms, the iscount is not enabled. The timer and counter are stopped. Rpin_out is logical 0

. Return to step 0.

Debounce_module.v is a combination module. Module combination. The location of the signal connection is clearly annotated.

Completion diagram:

Conclusion 3:

Experiment 3 is the combined modeling of "functional modules. The modeling method complies with the "One module, one function" principle, and adds the description of "graphics" and "Connections" in the most direct way, it improves the "solution" of the "completion module" and the "possibility" of the design ".

Of course, the benefits of "low-level modeling" are more than just here. As the modeling engineering degree increases, the advantages of "low-level modeling" will become more and more prominent.

Experiment 3 Configuration

Black gold FPGA model: Cyclone II ep2c8q208c8

The. V file in experiment 3.

The level after successful compilation.

The key resource used in experiment 3 is key1.

Expansion Board

Core Board

Link between the core board and the expansion board. In experiment 3, the Extended Board resource is key1, that is, pin3.

The LED resource used in experiment 3 is led1, that is, pin69.

Pin configuration as above. The pin configurations of CLK and rstn are no longer repeated.

Expand the graph after completion.

Experiment 4: deshake module 2

The difference between Experiment 4 and experiment 3 is output. In experiment 3, debounce_modulve.v pulls up the output when it detects the changes from high to low levels. However, when it detects the changes from low to high levels, it pulls down the output. In experiment 4, debounce_module.v, when the level changes from high to low are detected, pull the time of a clock and then pull down the output. When a level change from low to high is detected, only the shake action is performed, and the output has no effect.

Experiment 4 source code: Tutorial 4:

The difference between most of the source code and the experiment is that delay_module.v's "sequential operations in Imitation" code segment. As you can see from the code above, when the level changes from high to low are detected (line 1), step I will go to step 1. After a delay of 10 ms, increase the output, and then go to step 2. Step 2 will pull up and down and return to step 0. Similarly, when the level change from low to high is detected in STEP 0, step 3 is displayed. after a delay of 10 ms, STEP 0 is returned.