[Serialization] [FPGA black gold Development Board] Those things of OpenGL-low-level modeling imitation sequence operation (12)

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• Chapter 4 low-level modeling and sequential simulation

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Chapter 4 Basic Ideas for low-level modeling and sequential operation imitation 4.1

C language programming, in terms of understanding, we can be seen as "sequential operations ". Just like eating a series of steps, you can open your mouth, break the entrance, and swallow the meal. It is actually impossible to execute an image similar to "sequential operations" in the language of OpenGL. However, we can model the execution mode of "sequential operations", which is also called "sequential operations ". Basically, we need to implement a "sequential copy operation". Without structural modeling, the results would be terrible. However, "low-level modeling" has standards, structures, and organizational modeling methods. It is obvious that "low-level modeling" has advantages in implementing "sequential simulation operations.

We use the SOS signal experiment to illustrate the basic idea of "operating in imitation sequence. If the SOS signal experiment is implemented in C language, the method is as follows:

// Create the S function

Void s_function (void ){...}

// Create an o Function

Void o_function (void ){...}

// Create an SOS Function

Void sos_function (void)

{

S_function ();

O_function ();

S_function ();

}

// Call the SOS Function

Int main ()

{

Sos_function ();

Return 0;

}

First, create two basic functions s_function () and o_function, and then create a function sos_fucntion () to call the two basic functions in sequence. Finally, main () can directly call sos_function (). Because the C language is a high-level language, the "call function" and "function return" executed at the underlying layer are hidden.

So what should we do if we want to implement "sequential operations" using the language of OpenGL?

Lab 11: SOS signal 3

First, we need to build functional modules like S and O functions.

S_module.v

15th ~ The 45 rows are 1 ms counters. The first row defines a constant of 1 ms, 21 ~ 31 rows are 1 ms timers, but the iscount mark Register enables this timer (28 | 30 rows ). 35 ~ The 43 rows are counters, and the counting result is controlled by the rtimes register (40 rows ).

47 ~ Line 51 is the declaration of each register. The I register controls the execution steps (47 rows). The rpin_out register is used to drive the pin_out output (48 rows). However, isdone is used to drive the output of done_sig (51 rows ).

(Note that the rtimes reset value is a random value except 0. Note that rows 62nd to 79 are the core part of s_module.v, and rows 62nd are the "enable" function, s_module.v can work after start_sig is increased.

65 ~ The 69 rows are "latency writing". When I is equal to 0, 2, and 4, the rpin_out register is set to logic 1. However, the delay is 100 ms (67 rows ). On the contrary, when I is equal to 1, 3, and 5, the rpin_out register is set to logic 0, and the delay time is 50 ms (71 rows ).

The preceding method is as follows:

When I is equal to 0, because the if condition is not true (66 rows), iscount is set to 1, and rtimes is assigned 100. When iscount is set to 1, the timer starts counting and generates a timer (28 rows ),

Counter (35 ~ 43 rows) Every 1ms interval will count once (42 rows) until the count is the same as the rtimes Value

(40 rows), and the return value is 0. At the same moment, the IF condition is true, and iscount is set to logic 0. The rpin_out register is increased at the same time, and the I register increments to indicate the next step (66 rows ).

At last ~ Line 77 generates a high-pulse done_sig.

O_module.v

The difference is basically the same as s_module.v. The difference is that the delay is long (67 rows ). Because we know that O's moss password is longer than S's moss password.

Sos_control_module

Next, we will establish a control module sos_control_module.v that controls the execution order of s_module.v and o_module.v.

In 20 ~ Line 21 defines the mark registers of ISS and ISO. ISS is used to drive s_start_sig (57 rows), and ISO is used to drive o_start_sig (58 rows ).

In ~ Row 53 is the core part. The 32 rows are "enable". As long as start_sig is not high, this module will not work.

We know that the sequence of SOS generation is to first generate S, generate O, and then generate S, but 35 ~ This is the case for 45 rows of "sequential operations like imitation.

Assume that:

When I is equal to 0, because the if condition is not met (36 rows), the ISS register is set to 1 (37 rows ). Then sos_module.v will wait for the High-pulse feedback from s_done_sig. When s_done_sig reports a high pulse, that is, s_module.v has completed the operation. This also means that the if condition is met (36 rows ). The ISS flag register is then pulled down, and the I register increments to indicate the next operation.

The above situation will be executed until 42 ~ 43 rows. At last, done_sig generates a high pulse.

Two-dimensional and multi-dimensional problems:

Before s_module.v, o_module.v, and sos_control_module.v are combined, there is a problem of dual-meter or multi-definition. We can see from the figure that the pin_out outputs of s_module.v and o_module.v share the buzzer resources, but we must understand the fact that "only one output at a time. To effectively coordinate the output of pin_out, add a "selector" to control the output.

Sos_module.v

Is the combination module sos_module.v. The call to the module has start_sig and done_sig signals. However, at the output end, a "selector" is added to coordinate the output.

Lines 15th to 72 are basically the same as "Images. Instantiate s_module.v, o_module.v and sos_control_module.v, and connect them.

In the range of 62 ~ The 72 rows are the "selector" and the pin_out register is used to drive the pin_out output (65 rows ). In line 67, it indicates "change at any time ". However, s_start_sig and o_start_sig signals are used as the identification signals of selector. When s_start_sig is high, the drive pin_out output is the s_pin_out line. When o_start_sig is high, the o_pin_out drive is pin_out output.

But one thing to note is that there are 70th rows. Each selector requires a "default state". If this row is not added, many compilation warnings will appear.

Tutorial 11:

This experiment is mainly an example of a simple "sequential copy operation. The above modeling is completely an exemplary "sequential operation "-C LanguageDesign an SOS experiment.

The modeling of "sequential simulation" has a basic "modeling structure", that is, all modules have "start_sig" and "done_sig ". "Start_sig" is like a C language call command, and "done_sig" is like a C language return command. These two signals exist to facilitate the call of the module.

The last point is the "selector". The existence of the selector in the combination module is really necessary, because the module of "imitation sequential operation, there are usually two or multiple meanings of "output resources. However, the "selector" uses the "xx_start_sig" signal to achieve "Coordinated Control ". Therefore, "Combination module" is not only a work of "Combination.

For the "Naming" issue, although "Naming" is not mandatory, I am very "recommended" to "understand" the "Naming" habit, rather than "Easy to compile ". If the "name" result is easy to understand and can be easily called with a short length, it would be better. However, it is often difficult to keep the best of both worlds. If you can do anything, "Naming" should be more inclined to "Understanding ".

Complete extension diagram:

Conclusion:

Is it estimated that many readers are not used to the writing or modeling of "sequential imitation operations? For example, "what is the timing of calls from the previous module to the next module ?"

Assume that sos_control_module.v calls s_modue.v. At the beginning, sos_control_module.v enables s_module.v. When s_module.v completes the operation, a high pulse of completion signal is generated.

However, the signal generation takes two minutes. At the first time, s_module.v raised the xx_done_sig signal. At this moment, sos_control_module.v detected a high pulse, and then it would "not enable" s_module.v, however, this operation must be executed at the next time. At the second time, xx_done_sig has been lowered and assigned a value of 0 to I. At this moment, sos_control_module.v cannot execute s_module, however, the operation s_module.v has been completed, basically without any impact.

Basically, I have made many adjustments and modifications to the problem of "sequential imitation operations. If the reader asks for more detailed information, I suggest that the reader review this note by learning the "Maid modeling technique-low-level modeling-imitation sequential operations (Train of Thought. This note is a note completed by the author while debugging and modifying the "Operation in imitation order", so the record is more detailed.

The modeling method of "Imitation sequential operation" may make readers who touch it for the first time quite unaccustomed. I hope readers can patiently think and understand it. In fact, the understanding of "Imitation sequential operations" is very simple, because "low-level modeling" has fully simplified the difficulty of modeling. If you have mastered the Basic Experiments in Chapter 2 and Chapter 3, it is estimated that there is no difficulty.

Demonstration on experiment 11:

In this demonstration, we will call sos_module.v completed in experiment 11.

Sos_module_demo.v

The isstart flag register is defined in line 13 and is used to enable sos_module.v (29 rows ). At the beginning, isstart is reset to 1, and sos_module.v is enabled and then started to work (17 rows ). After sos_module.v is completed, a high pulse is returned by done_sig. When this pulse (18 rows) is detected, isstart is set to logic 0, and sos_module.v is silenced.

In other words, sos_module.v will be operated once at the beginning, and then the operation will be stopped after the operation is completed.

Demonstration on experiment 11:

In this demonstration, it fully represents the convenience of calling modules by start_sig and done_sig.

Conclusion:

The demonstration in experiment 11 demonstrates the call to the completed "Operation in imitation sequence" module.

Summary:

In this chapter, I used a simple experiment to demonstrate the key points of "sequential simulation" modeling.

First, the basic idea and basic modeling method of "sequential imitation operations.

Second, the importance of start_sig and done_sig

Third, there are two or more problems in "sequential operations like imitation.

Fourth, the role of the "selector" in the combination module.

For the characteristics of "low-level modeling", when it is integrated with the modeling of "quasi-sequential operations. The idea of modeling can be the same as the idea of sequential operation programming. In other words, what you want to design in C language can also be used in "modeling in the language of OpenGL ".

Of course, you can also regard it as a low-level modeling method, but don't forget that "low-level modeling" focuses on more structural and understandable modeling techniques. Because "Imitation sequential operation" is nothing more than a modeling method that imitates "sequential operation", rather than completely building "the habit of designing C Language" on the modeling of the Tilde HDL language. The C language and the OpenGL language are two languages, and they are completely unavailable. If there is no powerful"CodeStyle ", modeling of" Imitation sequential operations "is basically a nightmare. Therefore, to some extent, "low-level modeling" can be well qualified for this job.

In terms of the "low-level modeling" principle, "one module and one function ". We can assume s_module.v contains s_function (), and o_module.v contains o_function (). In addition, "control execution order" is required. sos_control_module.v "control module" contains "control execution order ". At last, the combination module and the problem of solving the two instruments are the functions of the combination module. The combined module sos_module.v can be regarded as sos_function (). Readers try to ask themselves what is the significance of this "criterion" in this series of Modeling Processes? Without complying with the "low-level modeling" principle, the modeling of "sequential simulation" is a tough task.

finally, another point is the iconic module structure (start_sig and done_sig) of "sequential operations in Imitation ). From the perspective of "sequential operations", they are like "Call commands" and "Return commands ", however, the existence of "sequential operations like imitation" is not to build a "microprocessor" to integrate "C language design habits ". After all, we need to use the language "not to lose the features of the language itself, but to operate in an exemplary order. The use of "start_sig" and "done_sig" is a major feature of "sequential simulation" modeling, or is required.