[Serialization] [FPGA black gold Development Board] those issues in the FPGA-digital tube circuit drive (8)

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3.1 experiment 7: digital tube circuit drive

If you have studied single-chip microcomputer, do you know more or less about digital tubes? I will not repeat these basic knowledge, because there is already a lot of such information on the Internet. I have learned different driving methods, but from the circuit of the black gold Development Board, I think the designer is really good job. Because the circuit carried by the black gold development board is very basic, it has learning value.

Digital tube is a common Yang, but with a PNP tube to respond to the drive and control column scanning (sel0_t and selw.t ). In addition, all the "segment selection signals" (LEDA .. ledh) of digital tubes share the same pin. In conclusion, all digital signals are "low-level effective ".

The purpose of experiment 7 is to design a project with a maximum of 99 numbers on two digital tube resources. The actual method is synchronous dynamic scanning. It is estimated that "dynamic scanning" should have been learned. "synchronous dynamic scanning" refers to synchronous scanning of "Row signal" and "column signal. In other words, it is a real parallel operation.

Let's first look at the modules to be created in experiment 7:

The combination module exp07_top.v in experiment 7 is composed of four functional modules. Each function module is named like itself.ProgramThe design concept is as follows:

The "Ten bit acquisition module" receives a maximum of 99 numbers. The module then performs the bitwise operation, divides the ten digits into different parts, and then outputs the independent signal lines ten_data and one_data. In the middle is the "SMG overweight module", which converts the number of binary components into SMG code. Ten_data and one_data are converted and output by ten_smg_data and one_smg_data. Finally, the "Scan module" smg_can_module.v is used to execute "synchronous dynamic scan" to light up the digital tube.

3.1.1 number_mod_module.v

The design of "number_mod_module.v" is very simple. It is to use the mathematical operators "%" and "/" to obtain ten people and everyone respectively. The maximum input value is 00 ~ 99.

The source code above is relatively simple. However, the readers may be confused. In 16th ~ Line 17 declares a 32-bit register for the purpose ~ 28 rows are used to store the ten and one digits of the result. But why is it 32-bit?

I remember that in Quartus II 9.0, the "divisor" can be defined by myself. However, in version 10.0, these options disappear. In particular, it is better to say "default" when it disappears. By default, the "divisor" and "remainder generator" are 32-bit output. However, after "Compilation", the compiler will "automatically optimize" the most suitable bit width. So that's why ~ The statement in line 17 is 32 bits! In addition, the "divisor" and "remainder". V files will be "automatically added" under the level of the original. V file.

After compilation, the "divisor" and "remainder generator"

Compiled. V File

3.1.2 smg_encoder_module.v

The design is still very simple, 17th ~ The 20 rows declare the constant of the SMG code. 24th ~ Line 45 is a Code adding operation (32 rows) for "ten digits ). 50th ~ The same operation is performed on 71 rows, but for single-digit (58 rows) rows ). 75th ~ Line 76 is the output.

3.1.3 smg_scan_module.v

Smg_scan_module.v is undoubtedly a combination of row_scan_module.v and column_scan_module.v. Whether it is the "Row scan module" or "column scan module", the scan frequency is set to 50Hz.

Column_scan_module.v

Because experiment 7 requires two digital tube resources, assuming that each digital tube can be enabled for 10 ms, the time occupied by the two digital tubes is naturally 20 ms. In other words, it takes 20 ms to complete a scan.

However, column_scan_module.v performs "column scan ". To put it simply, you can use different digital tubes every 10 ms.

Row 3 declares a constant of 10 ms. 16th ~ 24 rows are 10 ms timer, while 28 ~ 36 rows are used to control the scanning order. Register t indicates the current scan, whether it is 0 or 1 (0th digital tubes or 1st digital tubes ). 40th ~ Row 61 is the specific operation of column_scan_module.v. When T is equal to 0, 0th digital tubes are enabled (low). When T is equal to 1, 1st digital tubes are enabled (low ).

Row_scan_module.v

After understanding column_scan_module.v, we can understand that row_scan_module.v literally means "Row scan. Based on column_scan_module.v, we know that this module enables different digital tube resources every 10 ms, while row_scan_module.v has similar functions. Row_scan_module.v outputs different SMG codes every 10 ms. For more information, seeCode:

16th ~ 40 rows, exactly the same as column_scan_module.v. In 44 ~ Line 55 row_scan_module.v outputs different SMG codes every 10 ms. Output "ten_smg_data" (52nd rows) when T is equal to 0, and "one_smg_data" (53rd rows) when T is equal to 1 ).

Smg_scan_module.v

Smg_scan_module.v combination module. The code is relatively simple. Check the Code directly.

In general, the smg_scan_module.v function can be used to represent tables:

Time

Column Scan

Row Scan

Initialization

None

None

T0

0th digital tube Resources

10-digit SMG code

T1

1st digital tube Resources

Single-digit SMG code

Extended diagram:

3.1.4 exp07_top.v

Tutorial 7:

In our overall understanding, the reason why we naturally go from right to left is the effect of "graphics. Because "graphics" describes experiment 7 as "output from left to right ". After we understand the functions of each module, we can connect to each other to understand the operations of the entire module.

Extended diagram:

Experiment 7 conclusion:

Experiment 7 is a complete and elementary "low-level modeling", and the modeling conditions fully comply with the "low-level modeling" principle.

Although "low-level modeling" involves a large amount of modeling, it makes the design more flexible. In addition, "one module and one function" and "connection relationship" greatly improve the overall solution.

The design of experiment 7 is only for "2 digital tube resources". Of course, you can also extend it to support "6 digital tube resources" and "0 ~ 999999 ", or modify other.

Demonstration in experiment 7:

The demonstration in experiment 7 is to create a 0 ~ 15. Then the counter will directly drive the number_data input signal of exp07_top.v.

Demonstration of experiment 7:

The second row defines the constant of 1 s, while the second row defines the constant of 14th ~ 41 is a 15 s counter. 43rd ~ The 54-row instantiation exp07_top is u1. In row 49th, The counter_sec is used to directly drive the exp07_01 input port.

Extended diagram:

Experiment 7 demonstration conclusion:

This is just a simple demonstration. The demonstration mainly refers to calling the exp07_top guide.