Setting and use of interval timer in TCP transmission protocol

I. Summary

As mentioned in the blog "diy_de2 dm9000a Nic debugging routine series (4) -- TCP/IP implementation based on nichestack protocol stack", when using the system to build the niosii soft core, an interval timer core is required for the uC/OS II system. The interval timer kernel has multiple modes. At that time, a simple periodic interrupt mode was selected, and data transmission was normal. However, when Video Transmission Based on the UDP protocol is completed (the hardware configurations of the two are identical), network transmission cannot work, finally, the interval timer core problem is determined,Select full-featured ModeAnd the network works normally. The following describesInterval timer core.

 

Ii. Overview of interval timer Core

This time counter is a time counter designed by a processor based on the aveon architecture. This counter has the following features:

(1) 32-bit and 64-bit counts;

(2) functions such as counting start, counting stop, and resetting counter;

(3) Two technical modes: one-time count and continuous count;

(4) counting cycle register;

(5) When the counter is counted to 0, you can enable or disable the trigger of the interrupt (IRQ );

(6) It can be used as a watchdog, that is, when the counter never reaches 0, system reset is generated;

(7) generate a periodic pulse. When the counter counts 0;

(8) It can be used in 32-bit or 16-bit processors. For example, a 16-bit NiO and a 32-bit NiO II.

 

Iii. instantiate the interval timer core in the FPGA Builder

  3.1 Count cycle ( Timeout period )

The count cycle determines the value of the period counter (period registers. The processor can change the counter value through the write cycle counter (period registers. Or when writeable period is disabled, the period counter (period registers) cannot be changed through the write operation of the processor. At this time, the period counter can only be a fixed period Count value that cannot be changed.

The interval timer counting cycle is an integer multiple of the system clock cycle. The actual clock cycle can be calculated as follows:

(1) obtain the system clock. The clock that drives the interval timer. Generally, it is the same as the niosii clock.

(2) Multiply the 16-bit and 16-bit values in the cycle counter with the count cycle obtained in the clock period.

3.2 Count size ( Counter size )

This setting determines the Bit Width of the counter. It can be set to 32-bit or 64-bit. A 32-bit counter contains two 16-bit registers, while a 64-bit counter contains four 16-bit registers. This setting is also applied to snap units.

3.3 Hardware options ( Hardware counter size)

(1) simple periodic interrupt-this setting is used to only need a counter with an interrupt (IRQ. In this mode, the counting cycle is fixed and cannot be changed by software, and the counting cannot be stopped but the interruption (IRQ) can be disabled.

(2) full-featured-this configuration applies to a counter that can be changed by the processor, can be changed by a variable counting cycle, and its start and stop can be changed.

(3) Watchdog-applicable to situations where the system requires a dog. When the system stops responding, this configuration can reset the system.

(4) M m-custom.

3.4 Register ( Register ) Settings

(1) writeable Period -- If this option is selected, the primary peripheral (nioii) can modify the count cycle by using the period register (period registers. If this option is not selected, the count cycle is determined to be (timeout period) and cannot be changed. The period register (period registers) no longer exists.

(2) readable snapshot -- if this item is selected, the main peripherals (niosii) can read the current Count value. If this option is not selected, the primary peripheral can only know the Count status by querying the Status Register or the interrupt (IRQ) flag. At this time (SNAP registers) does not exist, there will be uncertain values when reading this register.

(3) start/stop control bits -- if this item is selected, the primary peripheral (nioii) can start and stop the counter by using the control register. If this option is not selected, the counter is in continuous count mode by default. It is worth noting that when the system reset on timeout (watchdog) is enabled, the (start) bit in the control register is set, regardless of the status of the start/stop control bit.

3.5 Signal output option ( Output signals )

(1) Timeout pulse (1 clock wide) -- if this item is selected, the counter generates a signal port (timeout_pulse ), this signal port generates a high level of the system clock cycle when the counter is reduced to 0. If this option is not selected, the counter does not generate this signal port.

(2) system reset on timeout (watchdog) -- if this item is selected, the counter generates a reset signal port (resetrequest port) this signal generates a high level of the system clock cycle when the counter is reduced to 0. If this option is not selected, the signal port does not exist.

3.6 Configure the counter as a watchdog

If you want to use a watchdog, make the following options.

(1) presets: Select watchdog;

(2) Change timeout period to the required time

(3) writeable period prohibited;

(4) readable snapshot disabled;

(5) start/stop control bits is prohibited;

(6) Disable timeout pulse;

(7) Enable system reset on timeout (watchdog.

The watchdog is disabled after the reset. Then, the processor writes 1 to the Start bit of the control register and enables the watchdog count. Once enabled, the dog cannot end. In order not to reset the system, the processor should reset the Count value at regular intervals.

PS: For more detailed documentation, refer to the official datasheet.