Several clocks in the STM32 Systick, FCLK, SYSCLK, HCLK

Use the clock source to generate the clock!

In STM32, there are five clock sources for HSI, HSE, LSI, LSE, PLL. ①, HSI is a high-speed internal clock, RC oscillator, frequency of 8MHz.

②, HSE is high-speed external clock, can connect quartz/ceramic resonator, or connect
External clock source with a frequency range of 4mhz~16mhz.
③, LSI is a low-speed internal clock, RC oscillator, frequency of 40kHz.
④, LSE is a low-speed external clock, the frequency of 32.768kHz quartz crystals.
⑤, PLL is a phase-locked loop multiplier output, the clock input source can be selected as HSI/2,
HSE or HSE/2. The multiplier can be selected as 2~16 times, but its output frequency is the most
No more than 72MHz in size.

The 40kHz LSI (Low speed internal clock) is used by the independent watchdog IWDG, and it can also be selected as the clock source for the real-time clock RTC. In addition, the clock source of the real-time clock RTC can be selected by the LSE (low-speed external clock) or the 128-way of HSE (high-speed external clock). RTC's clock source is selected via rtcsel[1:0].

There is a full-speed USB module in the STM32, and its serial interface engine requires a clock source with a frequency of 48MHz. The clock source can only be obtained from the PLL output, optionally 1.5 or 1, that is, when a USB module is required, the PLL must be enabled, and the clock frequency is configured to 48MHz or 72MHz. (armjishu.com)

In addition, the STM32 can choose a clock signal output to the MCO foot (PA8), you can choose to output the PLL 2, HSI, HSE, or system clock.

The

system clock SYSCLK a maximum frequency of 72MHz, which is the clock source for most parts of the STM32. The system clock can be output by the PLL, HSI, or HSE, and it is used by the AHB divider for each module, and the AHB divider can be divided into 1, 2, 4, 8, 16, 64, 128, 256, 512. The clock for the AHB divider output is given to 5 modules using: ①, HCLK clock for AHB bus, kernel, memory, and DMA use.
②, the system timer clock (Systick=sysclk/8=9mhz)
for the STM32 chip is ③, and the free-running clock is sent directly to cortex running. "Armjishu Note: The FCLK is a free-oscillating processor clock for the processor that is used to sample interrupts and timing the debug module. When the processor sleeps, the FCLK guarantees that the interrupt and trace hibernation events can be sampled. The CORTEX-M3 core "free-running clock" running FCLK. "Free" behaves when it does not come from the system clock HCLK, so FCLK also continues to run when the system clock is stopped. FCLK and HCLK are synchronized with each other. FCLK is a free-oscillating hclk. FCLK and HCLK should be balanced against each other to ensure the same delay when entering CORTEX-M3. "④, give APB1 divider. APB1 Divider can choose 1, 2, 4, 8, 16 divided, its output for APB1 peripheral use (PCLK1, the maximum frequency 36MHz), the other way to the timer (timer) 2, 3, 4 times frequency multiplier used. The multiplier can choose 1 or twice times, the clock output for Timers 2, 3, 4 use.
⑤, to the APB2 divider. APB2 crossover can choose 1, 2, 4, 8, 16, the output of the APB2 peripheral use (PCLK2, the maximum frequency 72MHz), and the other way to the timer (timer) 1 time multiplier used. The multiplier can choose 1 or twice times, the clock output for the timer 1 use. In addition, the APB2 divider has one output for the ADC divider, which is used for the ADC module. The ADC divider can be divided into 2, 4, 6, 8.

The above mentioned 3 kinds of clocks fclk, HCLK and PCLK, simple explanation is as follows: FCLK to supply the CPU core clock signal, we say CPU frequency is Xxxxmhz, refers to this clock signal, corresponding, 1/FCLK is the CPU clock cycle HCLK provides clock signal (AHB for advanced High-performance Bus) for excellent high performance bus (AHB bus peripherals), and HCLK:AHB bus clock, which is divided by the system clock SYSCLK, and generally does not divide, equals the system clock, HCLK is a high-speed peripheral clock, which is for external devices, such as memory, Flash. The PCLK provides a clock signal for the excellent high performance peripheral bus (APB Bus peripherals) (where the APB is the Advanced peripherals bus).

In the above clock output, there are many with enable control, such as AHB bus clock, core clock, a variety of APB1 peripherals, APB2 peripherals and so on. When you need to use a module, be sure to first enable the corresponding clock.

Note that the timer multiplier, when the division of the APB is 1 o'clock, its multiplier value is 1, otherwise its multiplier value is 2.

The devices connected to the APB1 (low Speed peripherals) are: Power Interface, Backup interface, CAN, USB, i2c1, I2C2, UART2, UART3, SPI2, window watchdog, Timer2, Timer3, Timer4.

Note: Although a USB module requires a separate 48MHz clock signal, it should not be a clock for the USB module to work, but simply a clock that is available to the Serial Interface Engine (SIE). The clock that the USB module works on should be provided by APB1.

The devices connected to the APB2 (high-speed peripherals) are: UART1, SPI1, Timer1,
ADC1, ADC2, all normal IO ports (PA~PE), second function IO port.

[Caption Id= "attachment_2541" align= "Alignnone" width= "516" caption= "STM32" Hclk and FCLK diagram "] [/caption]

is the clock system structure in the STM32 User manual (on page 14th of Stm32f103cde_ds_ch_v5.pdf, or 47th of the STM32F10XXX Reference manual _cn.pdf), which allows you to

[Caption Id= "attachment_2542" align= "Alignnone" width= "847" caption= "STM32" clock system structure "]

Master the STM32 clock system in general.

Several clocks in the STM32 Systick, FCLK, SYSCLK, HCLK