This paper interprets the SHARC clock system clkin: Clock input. pre-divider: Front dividerPost-divider: Rear divider CCLK: Kernel clockPCLK: Peripheral Clock
Register Overview
Power Management Control Register (pmctl). Governs the operationof the PLL and configures the PLL settings.
Power Management Control Register 1 (PMCTL1). This register controls the various peripheral ' s clocks.
Clock Control: Programmable registers are mainly available in two pmctl and PMCTL1. The system clock graph shows that the system clock is provided by Clkin, the Clkin has two places, and one is entered into the PLL by the input clock divider;The other one is connected to the output clock generator (rear divider). The former is fed into the PLL for octave, and the latter is to make the system run again bypass mode (that is, the kernel works on Clkin). Clkin through the input clock divider, the divider in the use of clock masterpiece pre-divider, controlled by the indiv bit of the PMCTL register, there is only one option, when indiv=1, the input clock is divided by 2, but indiv=0, the input clock is not divided. The clock passes through the pre-divider and then to the phase detector (phase detector), the phase detector in the phase-locked loop, the function is to detect the input signal and the output signal of the difference between phases, and the detected phase difference signal to the UD (t) voltage signal output, the signal is filtered by the low-pass filter to form a voltage controlled oscillator control Control the frequency of the oscillator output signal. The programmable functions of the clock system include: input clock divider enable, post divider enable, system clock selection, multiplier factor selection. the key to the programmable clock system is that it must work in bypass mode as long as it affects the operation of the output clock generator. PMCTL1 Peripheral Clock enable: Each bit corresponds to the corresponding peripheral, the default value is 0, 1 turns off the peripheral clock. Programming Flow:1, first let the system work in bypass mode. (bypass mode, that is, the kernel works under the Clkin clock)2, such as 4,096 clock cycles. 3, set the pre-divider (INDIV), set the PLLM, Plld. 4, such as 4,096 clock cycles. 5, Exit bypass mode, wait 15 cycles.
intI, pmctlsetting; //Set indiv bit in Pmctl registerpmctlsetting = *Ppmctl; Pmctlsetting|=Indiv; *ppmctl=pmctlsetting; //Program PLLs multiplier to same value as CLK_CFGX pins/previously programmed value in software 厖*ppmctl =pmctlsetting; //Then place the PLL in bypass modePmctlsetting |=PLLBP; *ppmctl =pmctlsetting; //Wait for recommended number of cycles for(i=0; i<4096; i++) NOP; //bring PLL out of bypass mode by clearing PLLBP bit*ppmctl ^=PLLBP; for(i=0; i< -; i++) NOP; Pmctlsetting= *Ppmctl; //Clear the previous PLL multiplierPmctlsetting &= ~PLLM63; //Clear the Indiv bitPmctlsetting &= ~Indiv; //or set the INDIV bit//*pmctl |= indiv;*ppmctl=pmctlsetting; //clkin= MHz, multiplier=, divisor= 2, Cclk_sdclk_ratio 2.5.//FCCLK = (Clkin * 2 * M)/(N * D)//VCO frequency = 2*FINPUT*PLLM = 2*25*16 = <= Fvcomax (in MHz)//M = 1 to 1, N = 2,4,8,16 and D = 1 if indiv = 0, D = 2 if Indiv =pmctlsetting= pllm16| plld2| sdckr2_5|Diven; *ppmctl=pmctlsetting; Pmctlsetting|= PLLBP;//Setting the Bypass bitPmctlsetting^= Diven;//clearing the Diven bit*ppmctl= pmctlsetting;//putting the PLL into bypass mode//Wait for around 4096 cycles for the PLL to lock. for(i=0; i< the; i++) NOP; Pmctlsetting= *Ppmctl; Pmctlsetting^= PLLBP;//Clear Bypass Mode*ppmctl =pmctlsetting; //Wait for around, cycles for the output dividers to stabilize. for(i=0; i< -; i++) NOP;
SHARC Clock System
