Sheet of ARMv8 PMU EVENTS__PMU

I created a Google sheet for ARMV8 PMU events. After input all PMU events collect, it would generate some meaningful ratios in the next tab. That's helps to understand the performance of the tested application.

armv8-a PMU Worksheet

0x000	Architectural	Sw_incr	Instruction architecturally executed, condition code check pass, software increment
0x001	Microarchitectural	L1i_cache_refill	Attributable level 1 Instruction Cache Refill
0x002	Microarchitectural	L1i_tlb_refill	Attributable Level 1 Instruction TLB Refill
0x003	Microarchitectural	L1d_cache_refill	Attributable level 1 Data cache Refill
0x004	Microarchitectural	L1d_cache	Attributable level 1 data cache access
0x005	Microarchitectural	L1d_tlb_refill	Attributable level 1 Data TLB Refill
0x006	Architectural	Ld_retired	Instruction architecturally executed, condition code check Pass, load
0x007	Architectural	St_retired	Instruction architecturally executed, condition code check pass, store
0x008	Architectural	Inst_retired	Instruction Architecturally executed
0x009	Architectural	Exc_taken	Exception taken
0x00a	Architectural	Exc_return	Instruction architecturally executed, condition code check pass, exception return
0x00b	Architectural	Cid_write_retired	Instruction architecturally executed, condition code check Pass, write to Contextidr
0x00c	Architectural	Pc_write_retired	Instruction architecturally executed, condition code check Pass, software change of the PC
0x00d	Architectural	Br_immed_retired	Instruction architecturally executed, immediate branch
0x00e	Architectural	Br_return_retired	Instruction architecturally executed, condition code Check Pass, procedure return
0x00f	Architectural	Unaligned_ldst_retired	Instruction architecturally executed, condition code check Pass, unaligned load or store
0x010	Microarchitectural	Br_mis_pred	mispredicted or not predicted branch speculatively executed
0x011	Microarchitectural	Cpu_cycles	Cycle
0x012	Microarchitectural	Br_pred	Predictable branch speculatively executed
0x013	Microarchitectural	Mem_access	Data Memory Access
0x014	Microarchitectural	L1i_cache	Attributable level 1 Instruction cache Access
0x015	Microarchitectural	L1d_cache_wb	Attributable level 1 data cache Write-back
0x016	Microarchitectural	L2d_cache	Attributable level 2 data cache access
0x017	Microarchitectural	L2d_cache_refill	Attributable level 2 data cache Refill
0x018	Microarchitectural	L2d_cache_wb	Attributable level 2 data cache Write-back
0x019	Microarchitectural	Bus_access	Bus access
0x01a	Microarchitectural	Memory_error	Local memory error
0x01b	Microarchitectural	Inst_spec	Operation speculatively executed
0x01c	Architectural	Ttbr_write_retired	Instruction architecturally executed, condition code check Pass, write TOTTBR
0x01d	Microarchitectural	Bus_cycles	Bus cycle
0x01e	Architectural	CHAIN	For odd-numbered counters, increments the count by one for each overflow of the preceding even-numbered. For even-numbered counters there is no increment.
0x01f	Microarchitectural	L1d_cache_allocate	Attributable level 1 data cache allocation without refill
0x020	Microarchitectural	L2d_cache_allocate	Attributable level 2 data cache allocation without refill
0x021	Architectural	Br_retired	Instruction architecturally executed, branch
0x022	Microarchitectural	Br_mis_pred_retired	Instruction architecturally executed, mispredicted branch
0x023	Microarchitectural	Stall_frontend	No operation issued due to the frontend
0x024	Microarchitectural	Stall_backend	No operation issued due to backend
0x025	Microarchitectural	L1d_tlb	Attributable level 1 data or unified TLB access
0x026	Microarchitectural	L1i_tlb	Attributable level 1 instruction TLB Access
0x027	Microarchitectural	L2i_cache	Attributable level 2 instruction cache access
0x028	Microarchitectural	L2i_cache_refill	Attributable level 2 Instruction cache Refill
0x029	Microarchitectural	L3d_cache_allocate	Attributable level 3 data or unified cache allocation without refill
0x02a	Microarchitectural	L3d_cache_refill	Attributable level 3 data or unified cache refill
0x02b	Microarchitectural	L3d_cache	Attributable level 3 data or unified cache access
0x02c	Microarchitectural	L3d_cache_wb	Attributable level 3 data or unified cache Write-back
0x02d	Microarchitectural	L2d_tlb_refill	Attributable level 2 data or unified TLB refill
0x02e	Microarchitectural	L2i_tlb_refill	Attributable Level 2 instruction TLB Refill
0x02f	Microarchitectural	L2d_tlb	Attributable level 2 data or unified TLB access
0x030	Microarchitectural	L2i_tlb	Attributable level 2 instruction TLB access

Https://zhiyisun.github.io/2016/08/02/Sheet-of-ARMv8-PMU-Events.html