Shell ($) in makefile)

In makefile, shell commands are often used, and $ VaR are often used. What is the difference? The difference is big. Do not consider using $ VaR in the command line of the makefile rule to share the variables of makefile with the shell. Here, only the variables of makefile are read and extended, the value is passed as a parameter to a shell command. $ VaR is a variable defined in a shell command, rather than a makefile variable. In addition, if a rule consists of N shell command lines, and there is no ';' or '\' connection between them, there is no shell command associated with each other, variables cannot be shared with each other. Take the following example:

Makefile code snippet 1: Var = 3 target: prerequsite1 prerequsite2 echo $ VAR (1) Var = 4 (2) echo $ VAR (3) echo $ VAR (4)

In code segment 1, the result of (1) is 3. Obviously, makefile uses its own variable to extend $ VaR to 3 and then passes it to the shell command echo.

(2) is the first shell variable of an independent shell command. Its name is also called VaR and its value is 4, which does not affect the VaR in makefile.
(3) In (1), the value of VaR in makefile is still 3
(4) run $ VaR in makefile to get the following shell command:
Echo $ VaR is then handed to shell for explanation and execution. For this shell command, VaR is a defined variable, so the output result is a blank line.

Makefile code snippet 2: Var = 3 target: prerequsite1 prerequsite2 echo $ var; \ (1') Var = 4; \ (2') echo $ var; \ (3 ') echo $ VAR (4 ')

In code snippet 2, all shell commands are connected, and the execution result is changed:
(1') the result is the same as (1), and $ VaR is replaced with 3.
(2') results are the same as (2)
(3') Output 3, because although the shell contains the VaR variable, makefile must be extended first, and the extension result is Echo 3.
(4') output 4, because the extension result of makefile is Echo $ var, and the variable VAR is already in shell and its value is 4.

Similar examples are as follows:

Makefile code snippet 3: subdirs = tools examples SRC target: prerequsite1 prerequsite2 for dir in $ subdirs; do $ (make)-C $ dir; done

Make first expands the command:
For dir in tools examples SRC; do make-C $ dir; done
And then explain it to the shell. It can be seen that DIR is a variable in the shell.

In short, the $ var format is used when the party wants to reference the shell variable in the shell command of makefile.

In makefile, $ is also used for secondexpansion, that is, secondary extension, which is generally used as prerequsites.
For example:
. Secondexpansion (add this line to use this feature)
Main_objs: = Main. o try. O test. o
Lib_objs: = Lib. o api. o
Main Lib: $ ($ @ _ objs)

$ ($ @ _ Objs) The extension result of the first stage is $ ($ @ _ objs). The extension result of stage 2nd is: $ @ is replaced with main Lib, connect with _ objs to main_objs lib_objs. With the extension of $ outside, $ main_objs $ lib_objs is added, and the final result is main. O.
Try. O test. O Lib. o api. o