Embedded logic analyzer-sigbaltap II, separated from software simulation, embedded logic analyzer, multi-channel data testing, without external logic. Something nice
In this example, the sine wave, triangle wave, sawtooth wave, and square wave waveform data are used as a reference to briefly describe SignalTap II.
(1) create a new project with pin configuration: the RTL diagram is as follows:
(2) create a SignalTap II file
(3) set the signal name to be tested
(4) double-click the node to add the digital signal to be observed. Do not call the system clock, because this example uses the system clock as the sampling clock of the logic analyzer.
(5) Add the system sampling clock (similar to the oscilloscope sampling)
(6) set the sampling depth: Because the ESB/m9k is used, the sampling depth should be smaller than 9 KB. Here it is set to 2 kb.
(7) set the trigger position for sampling
(8) trigger method: (I am not very clear here, probably Mode)
(9) set the trigger input: select the trigger signal and trigger mode. Flag is used to trigger the enable signal, which is useless in actual engineering. It is only the enable signal of SignalTap II. It is triggered at a high level.
(10) Save and yes, re-compile, and bind with the project to download to device. Of course, you can also set
If you are too lazy to set the pin, do not allocate out signals, but CLK and rst_n must be analyzed because it is the system drive signal.
After the test is OK, cancel the Enable SignalTap II logic analyzer in BMP to streamline the cost design.
(11) set handware setup and link to Device
(12) download the sof file (of course, you can also directly download it in q ii)
(13) process-anturon analysis, automatic analysis
(14) observe the output signal and set it to a analog signal.
(15) Why is it so handsome ....
(16) after testing for a period of time, a bug may occur, but the logic edge cannot be aligned for a long period of sampling. After all, it is not so perfect.
(17) OK, byebye