Simulation of parallel data transmission over three bus protocols on ATmega8

Source: Internet
Author: User

 

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In the graduation project, we chose the AVR + PDIUSBD12 solution for the data collection system design. However, some of the AVR single-chip microcomputer do not have the automatic external addressing function. For example, we chose the ATmega16, so we need to simulate a data address bus timing.

Knowledge points:
1. The external data/address bus includes three types of buses: Data Bus, address bus, and control bus. The data bus is used for data transmission and the P0 port is used in 51 single-chip microcomputer. The address bus is used for external data address selection. Generally, the microcontroller can be extended to 16-bit addressing. The P0 & p2 port is used as the address I/O port in 51 single-chip microcomputer. The control bus is used for timing control. It contains the (ale_n rd_n wr_n psen_n) control line.
2. Bus Operation Process:
A. When ale_n is high, the selected data address can be changed, and the lower-and lower-sides of ale_n can lock the address
B. When rd_n or wr_n is low, data can be read or written to an external device.
C. psen_n is the chip selection enabling port, which is valid at a low level.
3. For the Working Sequence of the entire process, refer to the AT89S52. pdf documentation.

The program list implemented in ATmega8 is as follows:

Void output_d12 (uchar address, uchar data)
{
// * (Uchar xdata *) Address) = data;
Portd | = (1 <ale); // set ale H
Ddrb = 0xff;
Portb = address; // load address
Nop ();
Portd & = ~ (1 <ale); // reset ale L
Portb = data;
Portc & = ~ (1 <d12wr); // enalbe write
Nop (); // Waite some time
Nop ();
Portc | = (1 <d12wr );

}

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