Simulation verification of Cadence UPF low power flow

This article is to record the project process encountered in the Kit Kat, if there is missing or insufficient, please correct and add, thank you.

With the popularization and development of deep submicron technology, the leakage power consumption in the whole power consumption is more and more large, such as 45nm, has accounted for more than 60%, so low power solutions came into being. There is a standard low-power design process with a CPF (Cadence-dominated) and UPF (Synopsys-led), but the technical trend is UPF unification, so this article will provide some references for those who still use Ncverilog instead of VCS simulation tools.
There are currently four ways to reduce low power consumption: Multi-voltage domain, clock gating, power-off and dynamic voltage-frequency adjustment. The clock gating has a small impact on the verification, everyone should have been exposed, while the remaining three of the impact on the verification work, need to use the various EDA manufacturers of low-power solutions.

gossip says so much, so how does cadence use UPF for simulation validation of low-power processes?
The first step is to have the UPF file, to create a script based on the design requirements, to establish and manage independent voltage sources, to isolate, to establish level drift, etc., generally design or back-end personnel writing, verification engineer can also write, specific content reference IEEE 1801.
The second step is to add the power-up process to the simulation case and use the $SUPPLY_ON function for powering the corresponding VDD.
The third step is to embed the UPF into the emulation command, which is:
irun-lps_1801 sim.upf-lps_assign_ft_buf-lps_iso_verbose ...
or
Ncvlog ...
ncelab-lps_1801 Sim.upf-lps_assign_ft_buf-lps_iso_verbose ...
Ncsim ... The
related options are explained as follows:
①-lps_1801 filename: Specifies the UPF file that complies with the IEEE 1801 standard,
②-lps_assign_ft_buf: Specifies that the assign assignment is treated as buffer, Instead of the default wire, the advantage is that the signal entered from always-on domain and through power-down domain is Force x, which facilitates debug;
③-lps_const_aon: to the Power-down Domain and direct and always-on domain connected Tie-high or Tie-low constant, do not enable corruption function; The function is not used by default;
④-lps_enum_rand_ Corrupt: for user-defined enum type data, after power off, randomly select a value from the enumeration list as the variable value; Similar to this command there are-lps_enum_right,-LPS_IMPLICIT_PSO, etc., because not commonly used, do not introduce each;
⑤-lps_iso_verbose: Enable isolation of the log function, this general need to add;
⑥ ... For the
Other options, refer to Cadence's Low-power simulation guide.
Finally, run the simulation.

Finally, the verification method of the correctness and completeness of the low power process validation.
① increased low power process can not affect the accuracy of the chip itself, such as power off to reduce the chip power consumption, the shutdown and then open, the chip can also work. This part can be confirmed using the original self-check verification environment.
② using log file analysis, the above simulation command-lps_verbose and UPF files for the simulation output and low power related warning, error and assertion information, through the log file can check the correctness of the process;
③ Automatic Assertion Checker analysis, use the-lps_verify option to automatically check the power-down sequence (isolation, reset, power off) and the power-on process (de-isolate), such as the reset, which does not meet the timing requirements, will automatically error;
④ uses coverage assurance to verify completeness, generates a low power verification plan based on the UPF file using the-lps_vplan option, and obtains low power-related feature coverage through the coverage interface provided by the simvision;

Simulation verification of Cadence UPF low power flow