Sixth chapter, Memory hierarchy structure

Memory hierarchy

6.1 Storage Technology

6.1.1 Random access memory

random access memory is divided into two categories: static and dynamic

1. Static RAM

The basic storage circuit of static RAM is a trigger, each trigger holds a binary information, a storage unit consisting of several triggers, and a memory matrix consisting of several storage units, together with an address decoder and a read/write control circuit to form a static RAM. However, because the static RAM is the active circuit to maintain the data in the memory, therefore, consumes more power, the price is also high.

2. Dynamic RAM

Each bit of data requires only one capacitor to be treated with a transistor, compared to a bit in the SRAM typically requiring six transistors. For this reason, DRAM has a very high density, with a higher capacity per unit volume and therefore lower cost. But on the contrary, DRAM also has the disadvantage of slower access and larger power consumption.

3, the traditional DRAM

Two-bit array-based organization

6.1.2 Disk storage

1. Disk Construction

Platter
Surface : Two surfaces per platter
Spindle : center of disc, rotatable
rotational rate : usually 5400~15000/min
track : Concentric circles
Sectors : Each track is divided into a set of sectors
Data bits : Each sector contains an equal number of ~, typically 512 bytes
Gap : Stores the format bits used to identify sectors
Disk drives-disks-Rotating disks
Cylinder : The set of tracks equal to the center of the spindle on all disc surfaces

2. Disk capacity

Recording density: (bits per inch) the number of bits that can be placed in an inch of a track

Track density: (Road/inch) The number of tracks that can be in the one-inch radius from the center of the disc

Surface density: (for/square inches) record density * Track density

Disk capacity = (Bytes/sector) * (average number of sectors/tracks) * (number of tracks/surface) * (number of surfaces/platters) * (Number of discs/disks)

3. Disk operation

Access time = Seek time + rotation time + delivery time

Rotation time: maximum rotation delay = (1/rotation rate) * (60SEC*1000MS/SEC)

Average rotation delay = (1/2) * Maximum rotation delay

Transfer time: Average transfer time = (1/rotation rate) * (60sec*1000ms/sec) * (1/average sector/track)

4. Accessing the disk

The CPU uses a technique called memory-mapped I/O to issue commands to I/O devices. In a system that uses memory-mapped I/O, a block of addresses in the address space is maintained for communication with the I/O device, which is called an I/O port.

The CPU initiates a disk read by writing the command, logical block number, and destination memory address to the memory map address associated with the disk.

The CPU executes the store command on the address, initiating disk reads:
The first instruction is sent with a command word; the second instruction specifies the logical block number that should be read; The third instruction indicates the main memory address where the contents of the disk sector should be stored.
Direct Memory Access : The device can perform its own read or write bus transactions without the need for CPU interference. This data transfer is called DMA transfer
Basic idea: Interrupts are signaled to an external pin on the CPU chip. This causes the CPU to pause the work it is currently doing, jumping to an operating system routine. This program will record that I/O is complete and then return control to where the CPU has been interrupted.

6.2 Local Sex

1, the principle of locality: When the CPU accesses the memory, whether it is the access instruction or accesses the data, the storage unit that accesses is tending to gather in a small continuous region.

2. Three different types of locality: temporal locality (temporal Locality): If an information item is being accessed, it is likely to be accessed again in the near future. Program loops, stacks, etc. are the reasons for the time locality. Spatial locality (spatiallocality): The information that will be used in the near future is likely to be near the spatial address of the information currently being used. Sequential locality (Order Locality): In a typical program, most directives are sequential, except for the transfer class directives. The proportion of sequential and non-sequential executions is roughly 5:1. In addition, access to large arrays is sequential. Sequential execution of directives, continuous storage of arrays, etc. are the reasons for order locality.

3. Locality of Instruction

The instructions in the loop body are executed in sequential memory order, so the loop has good spatial locality, because the loop experience is executed several times, so it also has good time locality.
Code that differs from an important property of program data cannot be modified at run time.

6.3 Memory Hierarchy

1. Cache Hit

If you need access to block D in the k+1 layer, if D is already cached on level K, it is called Cache hit. In this way, the Block D from the K-layer is larger than the k+1 layer.

2. Cache Misses

If D is not in the K level, then the cache is not hit, then the Block D is removed from the k+1 layer storage and placed in the K layer. You may need to replace the existing blocks in the K layer. The replacement strategy is: random, least recently used, and so on.

Need to have something to manage the cache, such as how to partition the block, how to transfer the block between the levels, determine whether the hit, do not hit how to handle, write back the data when it should be handled.

Are issues that need to be considered, hardware management such as cache, and software management such as virtual memory can also be used.

3, the management of the cache

i) Related assumptions

Assuming that the memory address has m-bits, there are m=2m different addresses.

A cache is partitioned into s=2s cache set,

Each group contains an E cache line.

Each cache line consists of a b=2b byte block, a valid bit, and a t=m-(b+s) tag bit.

The size of a high buffer zone C = S * E * B.

II) How to access the cache

When you want to access a byte in memory, the given access address of the M-bit, the first T-bit represents the marker bit, the middle s bit is the group index, and the last B bit is the block offset.

III) when the cache is not hit

When the cache is not hit, the blocks in the memory need to be placed in the corresponding group of the cache.

If the rows in the group have data, you need to replace the policy: Lfu or this LRU (don't want to elaborate)

IV) Three ways to divide the cache

Divided into direct mapping cache, group-linked cache, full-phase cache

If the value of S,E,B is specified, the cache partitioning method is determined.

A mapping relationship is also established between the cache block and the storage block.

Resources

1, "in-depth understanding computer system" textbook sixth chapter

2, 51cto.com

3, ZENGXG14 's Blog

4. Baidu Encyclopedia

Summary of this chapter

There is a brief introduction to RAM and ROM in the digital logic circuit. But not specifically, through this chapter to learn about the classification of memory, working principle, and how to improve performance and other aspects of knowledge.

Sixth chapter, Memory hierarchy structure