Smart terminal dual-Processor Architecture

Overview

Smartphones both contain two processors. The "Dual Processor" mentioned here is not two microprocessor kernels, but two processor platforms-application processors and baseband processors. Essentially, a smart terminal includes multiple microprocessor kernels, in addition to the control kernel of the 4-core, 8-core, and baseband processor of the application processor, DSP, and power management of the two, it also includes RF chips, WiFi, Bluetooth, GPS, touch screen, gyroscope, etc. Of course, the baseband processor may be integrated with RF chips and WiFi. An application processor is a master processor, which manages all peripheral devices, including baseband processors. This article only describes the architecture of application processors and baseband processors in smart terminals.

As the master controller, the application processor AP has powerful processing and computing capabilities. It runs Windows 8, Android, IOS, and other operating systems, user interfaces, and applications. The baseband processor BP is controlled by the real-time operating system and runs on another separate CPU to Implement air interface and communication functions, including GPRS, edge, 3G & HSDPA, and LTE protocol stacks.

The DBB (Digital Baseband Chip) of the baseband processor is used to complete the/D, D/A conversion of voice signals, encoding and decoding of digital voice signals, channel coding and decoding, and timing control of the baseband processor. The analog baseband (ABB) Voice Signal pin communicates with the audio codecs chip to form a voice channel during a call. The baseband processor must be coupled with peripheral circuits, such as audio chips, LCD, camera controllers, microphones, speakers, power amplifiers, and antennas) hardware circuit.

AP and BP interact with each other through advanced messaging interface. The communication control protocol can be at command and mbim. The advantage of separating the application processor from the baseband processor is that once the baseband processor is designed and certified well, no matter how the operating system and application software you use change, it can correctly execute the communication function. In addition, operating system and drive bugs do not cause devices to send catastrophic data to mobile networks.

In addition, BP has its own particularity. When the smartphone is in sleep mode, the AP can directly turn off the power supply of the LCD, camera and other peripherals, but BP must maintain the power supply to continue waiting for incoming calls, search for networks, etc, therefore, BP independently controls internal power management. When the wireless modem is idle, you can enter and exit the standby mode. In a separate architecture, the AP can perform power management negotiation through UART, gpio, and BP, while the Integrated SOC architecture provides dedicated power management.

(1) AP and BP separated Smart terminal Architecture

Smartphones on the market mostly adopt separate dual-CPU solutions: Communication baseband processors and multimedia function application processors act as two independent components for information interaction through inter-core communication. Similar to PC, this split architecture is equivalent to a peripheral of the main CPU ap-external wireless modem (BP ). Using a separate dual-CPU solution, the two processor platforms need independent and complete power management systems and their external memory, and their respective software upgrade interfaces (the AP needs to support the bypass and baseband boot guide functions ). The following is the hardware block diagram of the AP and BP separated smart phone of UART interface.

Smart phones designed with separate dual-CPU solutions have many problems, such as many components, large area, high costs, slow response speed, and software upgrade troubles. Generally, multiple analog switches are required between the AP and CP to switch the audio path, and audio codec must be added to the AP. The communication scheme between AP and CP must use the universal embedded interface gpio, UART, USB, SPI, and multi-port memory integrated with ic.

In the early stage, the physical interaction between AP and BP was realized through serial port (UART), and the power management between AP and BP was coordinated through general purpose input/outpu and gpio. When the mobile phone is idle, the AP and BP are all sleep to save power. For example, when a call is made, the AP uses gpio to wake up the BP and then sends the AT command through the serial port. When the call is made, the BP also uses gpio to wake up the AP and then sends the AT command through the serial port, notify the AP to start the ring and switch to the mobile phone interface. Obviously, UART, gpio, and at commands are used to coordinate the interaction between AP and BP, Which is inefficient.

In addition, the average UART transmission rate is 115k ~ 230 kbps, suitable for Low Speed 2G. Although the cell phone uses USB and SPI to replace UART, the efficiency has been improved, but the coordination between AP and BP still causes the bottleneck of cell phone work efficiency. For example, USB 2.0 can meet the speed requirements of edge, and later can meet the speed requirements of 3G, HSPA, but the USB scheme requires that the baseband processor must have a USB interface, the application processor can support USB host or usb otg equipment, the software processing is relatively complex and the USB power consumption is relatively large (USB-ULPI/hsic I interface reduces power consumption ). For specific inter-core communication methods, see "Inter-core communication methods"

(2) Smart terminal architecture integrated with the SOC Model

The baseband and application processor are used to combine two independent systems, its main disadvantages are many components, large area, low data exchange rate, high chip cost and high power consumption. To overcome these shortcomings, the SOC dual-in-one chip is the trend of the times. The division of labor between the AP and BP within the SOC is still clear. The difficulty lies in the difficulty of designing and manufacturing the SoC chip. The communication between the two usually relies on shared memory. The interaction between AP and BP information can be fast and effective, and the communication efficiency is very high, it solves the problem of inter-Processor Communication (data exchange) and has great advantages in big data transmission, but its technical difficulty is more complicated.

The two-in-one SoC chip features:

1. When all core cores are integrated into a single core, the division of labor between AP and BP is still clear.

2. It has an advanced clock management and power management system, and can independently control the clock frequency and power supply of each processor core, effectively controlling the power consumption of the system;

3. The system connects the core of each processor through the bus to share internal and external memory. The external memory is divided into three partitions: baseband, application, and sharing. The size of the memroy partition can be flexibly implemented as needed.

4. It can be integrated with a wide range of peripheral interfaces, such as dedicated LCD controller and camera interfaces, USB2.0 OTG controller, MMC/SD card controller, and digrf interfaces, this allows easy access to peripherals such as Bluetooth, WiFi, and GPS.

Take an SoC chip with three microprocessor kernels (ap arm kernel, bp arm kernel, and DSP Kernel used for physical layer and Audio Signal Processing) as an example to describe the basic architecture of SOC. The three-part Power Supply Management reason is unified clock power control unit control, and can independently clock and power management. The two arm cores have their own 16 K bytes of High-speed instruction buffer memory and 16 K bytes of data high-speed buffer storage. The core contains a memory management unit. The SoC chip has two shared RAM resources for data and information exchange. Among them, 16 K byte high-speed SRAM is shared by three processors, and the other 16 K byte high-speed SRAM is only shared by two arm cores, the soc pcu (processor control unit) and bus ruling tool can allocate read and write permissions and protect data for internal shared RAM. The memory shared by multiple processors can also be shared by several processors, and 16 K bytes of High-Speed SRAM can be added to AHB as the data buffer to improve memory access speed and system performance. The DSP acts as the L1 processor and the firmware to implement features such as protocol physical layer processing and audio processing.

The entire SOC model adopts a highly modular system architecture, which is very concise. It is designed with a small product size, low system costs, and easy to upgrade the system. During the upgrade, the entire architecture can be kept unchanged, and the processor can be simply changed (from arm11 to arm11, and the clock speed can be increased from MHz to MHz or higher) to enhance the processing and computing capability, it has good adaptability to the new trends and new applications of the mobile communication device market. When designing new products for mobile phone manufacturers, they can use the smallest design resources and reuse the basic design to the maximum extent, and quickly market the products in different market segments. The product system is stable.

At present, high-end mobile phones are integrating more and more functions (such as Bluetooth, handheld gps, WLAN, and mobile TV ). The demand for new features poses greater challenges to costs, power consumption, and product volume. Slim, lightweight, enhanced functions, and low cost are the future development trend of mobile phones. The dual-core architecture solution fundamentally satisfies the needs of the development of high-end mobile phones and demonstrates good development prospects and great potential.