CPU exceptions are divided into three main categories: Error class exception, trap class exception and terminating class exception
1 Error Class Exception Fault
After the CPU encounters such an exception, the CS and EIP (the instruction that is currently executing the error, not the next one) are stacked and then jumped into the exception handler, resumed to the original location after execution, and then re-entered if there is an error.
For example, a memory page exception is an error class exception, the CPU will jump to exception handling when it encounters an exception, replace the missing memory pages from the physical memory, and then restore the memory access instructions again.
2 Trap-Class exception trap
After the CPU encounters such an exception, the CS and EIP will be stacked, this EIP is the address of the next instruction of the current instruction, note that the next instruction may not be adjacent to the instruction, if the cause of the exception is the jump class instruction, the next instruction may be very far.
The usual int 3 we use is the trap class exception.
3 Terminating class Exception abort
This class of exceptions is used to report critical errors, such as hardware errors and system tables that contain illegal values or inconsistent states. Most termination exceptions may be caused by improper stacking operations, such as a mismatch between the stack and the stack, which the operating system handles as a program error, terminating the program that causes such exceptions.
4 Exception List
Vector number |
Mnemonic |
Type |
Describe |
Source |
0 |
#DE |
Error |
Except for 0 errors |
DVI and IDIV Instructions |
1 |
#DB |
Errors/Traps |
debugging exceptions, for software debugging |
Any code or data reference |
2 |
|
Interrupt |
NMI Interrupt |
Non-shielded external interrupts |
3 |
#BP |
Trap |
Breakpoint |
INT 3 Instruction |
4 |
#OF |
Trap |
Overflow |
into command |
5 |
#BR |
Error |
Array out of bounds |
Bound directive |
6 |
#UD |
Error |
Invalid instruction (no defined Directive) |
UD2 instruction (Pentium Pro CPU introduces this directive) or any reserved instructions |
7 |
#NM |
Error |
Math coprocessor does not exist or is not available |
Floating-point or wait/fwait directives |
8 |
#DF |
Terminate |
Double error (double Fault) |
Any instruction that could produce an exception, an unshielded interrupt, or a masked interrupt |
9 |
#MF |
Error |
Page error detected when transferring operand to coprocessor (page Fault) or segment not present, 486 and later integrated coprocessor, this error is reserved |
Floating point Directives |
10 |
#TS |
Error |
Invalid TSS |
Task switching or access to TSS |
11 |
#NP |
Error |
Segment does not exist |
Load segment registers or access system segments |
12 |
#SS |
Error |
Stack segment Error |
Stack operation or load SS register |
13 |
#GP |
Error |
Generic/General Protection exception, if an operation violates the rules in protected mode and the condition is not a different exception, the CPU is considered the exception |
Any memory reference or protective check |
14 |
#PF |
Error |
Page error |
Any memory reference |
15 |
Keep |
|
|
|
16 |
#MF |
Error |
Floating point Error |
Floating-point or wait/fwait directives |
17 |
#AC |
Error |
Alignment Check |
References to in-memory data (486CPU introduced) |
18 |
#MC |
Terminate |
Machine Check |
Error code and source related to model (Pentium CPU introduced) |
19 |
#XF |
Error |
SIMD Floating-point exceptions |
SIMD floating point instructions (Pentium III CPU introduced) |
20~31 |
Keep |
|
|
|
32~255 |
User-defined interrupts |
Interrupt |
Shielded interrupts |
external interrupt or int n instruction from Intr |
Software Debug--CPU Exception list