Some considerations in the design of low power (LPS) VLSI circuits

1. Non-retention Ram/register:

If the use of Ram/register itself in the Power-down state can not save its own state, then make sure that they will be in the power-up when the reset.

2. Output signal of Power-down part circuit in chip:

Power-down some of the output signals of the circuit can be used by other power-on parts of the circuit, then these signals must be processed. Avoid the X-value transmission to the power-on part of the circuit.

There are three kinds of processing methods: latch (the value of the output signal before the Power-down is saved), the connection high level (the value of the output signal will change to ' 1 ' after the Power-down), the connection low level (the value of the output signal will become ' 0 ' after Power-down).

These three settings can be done in the CPF (Common power format) file.

(CPF Syntax Reference: https://www.si2.org/?page=811)

3. State machine:

Similar to register, a state machine must be reset in the process of power-up. And the state machine in the design process must ensure its robustness, that is, once the accidental input, the state machine must be reset.

Some considerations in the design of low power (LPS) VLSI circuits