Each module:
(1) To enable, to act
(2) clock configuration (control data rate, different modules need to be executed separately)
(3) data input/output is completed in the buffer (register) and then controlled by the flag response of the corresponding status bit
(4) to allow the CPU to operate different modules of the request (introduce interrupt mechanism)
(5) If the CPU determines whether the module is starting to accomplish something, it is based on whether the corresponding state bit or interrupt bit has a potential change.
(6) to distinguish the transmission of different types of data, propose the concept of communication protocol
(7) Precise task of Timer/Counter completion time (baud rate, etc.)
(8) can read/write to the register, the premise is that the register has been defined by the corresponding macro address mapping
Some principles of single-chip microcomputer