Spartan6 series of articles: introduction and use of the gttransceiver

1. What is gttransceiver?

The gttransceiver is a type of FPGA line speed up to 500 Mb/s. the 6 Gbit/s Transceiver can be flexibly configured using FPGA's internal programmable resources, making it suitable for different needs such as Ethernet and sata1.0 interfaces, it serves the physical layer of various high-speed serial interfaces. For the spartan6 series, the gtpa1_dual contains two GTS transceiver, or two channels.

It is the internal structure of the gtpa1_dual. The lower part of the figure is worker er. After the worker is parallel to the bit stream of the serial input, perform synchronization primitive loss detection, comma character detection, 8B/10B decoding, etc. The upper part of the figure is transmitter, and the serial output of transmitter is opposite to that of receiver.

 

Figure 1 spartan-6 FPGA gttransceiver Diagram

It is the location map of gtpa1_dual in FPGA. In fact, FPGA's high-speed interfaces are generally located in the top part of FPGA. gtpa1_dual is a high-speed interface, and its placement is on the top of FPGA.

Figure 2 Location Map of the gtp-transceiver in the spartan6lx45t FPGA

As shown in figure 3, a gtdual contains two gtptransceiver gtp0, gtp1, and two PLL; the input reference clock of its PLL is optional when the gtcore is generated.

 

Figure 3two gttransceivers in one gtpa1_dual Tile

As shown in figure 4, pll0 and pll1 in gtpa1_dual can be connected to different clock sources or the same clock source 5 respectively. Two PLCs can generate two different clocks for use by gtpa1_dual. That is to say, the two transceiver of gtpa1_dual can run at different frequencies. Their protocols can be different. For example, one transceiver of gtpa1_dual runs the PCIe protocol and the other runs the SATA protocol.

 

Figure 4gttransceiver reference clock schematic 1

 

Figure 5 reference clock schematic 2

1.1. Several concepts that must be understood in the use of the gtp-transceiver

The spartan6 series's gttransceiver is placed in a dedicated bank. That is to say, in the spartan6 series, if a bank contains the GTPs pin, the bank will not contain the select Io pin.

One transmitter, one receiver, and one PLL constitute one Gbps lane;

Two gtp_dual lanes are formed;

Two gtp_dual instances form one bank;

 

1.2. Reset of gttransceiver

There are two methods to reset the gttransceiver: 1 is the power-on reset after FPGA is burned; 2 is to directly drive the gtpreset so that it is a high level for a period of time. It is the sequence chart of the internal reset of the GP transceiver.

 

 

Figure 6 gtpa1_dual reset hierarchy

If the gtpreset is valid, the resetdone immediately becomes invalid (lower). After the gtptransceiver reset is complete, the resetdone becomes valid (higher ).

 

Figure 7 reset Sequence Chart

 

1.3. Special pin function description of the gttransceiver

In essence, the gttransceiver is a analog circuit. In order to better design its PCB and so on, you must have a deep understanding of its pin functions.

Table 1gtpin description

Pins	Dir	Description
Mgtavcc	In	1.2 V is the internal analog and digital circuit power supply voltage of the gttransceiver.
Mgtavccpll0	In	1.2 V, not only power pll0, but also power the lane0 of gtpastmdual, so as long as the lane0 is used, the voltage pin needs to be powered.
Mgtavccpll1	In	1.2 V, not only power supply for pll1, but also power supply for lane1 of gtpa1_dual, so as long as lane1 is used, the voltage pin needs to be powered.
Mgtavttrcal	In	Power Supply for the terminal resistance Calibration Circuit, which is a basic power supply unit. This pin must be connected not only to mgtavtttx, but also to a 50Ω precision resistance and then to mgtrref.
Mgtavttrx	In	1.2 V, terminal circuit power supply of the receiver
Mgtavtttx	In	1.2 V, power supply voltage pin of the sending terminal
Mgtrefclk0p Mgtrefclk0n	In	Differential input clock of gtpa1_dual. If no, grounding is required.
Mgtrefclk1p Mgtrefclk1n	In	Differential input clock of gtpa1_dual. If no, grounding is required.
Mgtrref	In	Connect a 50Ω resistor to mgtavttrcal
Mgtrxp0/mgtrxn0 Mgtrxp1/mgtrxn1	In	Differential data input pin. if not used, grounded
Mgttxp0/mgttxn0 Mgttxp1/mgttxn1	Out	Differential data output pin. if not used, it should be left blank

Describes the recommended connection mode for the power supply of the gttransceiver. For the reason (Principle) of the connection, see table 1.

 

Figure 8 reference power connection mode

Spartan6 series of articles: introduction and use of the gttransceiver