Spartan6 series-spartan6 series-in-depth explanation of chip clock Resources

1. Clock resource Overview

The clock facility provides a series of low-capacitance, low-jitter Interconnect Lines that are ideal for transmitting high-frequency signals and minimizing clock jitter. These connection resources can be connected to DCM, PLL, and so on.

Each Spartan-6 Chip provides 16 high-speed, low-jitter global clock resources to optimize performance. These resources can be automatically used by Xilinx tools, even if the clock frequency is relatively low, it is still very important to use clock resources to eliminate potential timing risks,

Each Spartan-6 FPGA provides 40 ultra-high-speed, low-jitter I/O local clock resources (32 bufio2s and 8 bufpll) these IO Local clock resources serve Io serializer and de-serializer circuits.

The clock resources of the Spartan-6 FPGA are mainly composed of four types of connectors:

• Global clock input pin (gclk)
• Global clock multiplexing (bufg, bufgmux)
• Io clock buffer (bufio2, bufio2_2clk, bufpll)
• Horizontal clock wiring buffer (bufh)

There are two types of clock networks:

• Provides a global clock network with low-jitter clock resources for FPGA internal logical resources
• IO Local clock network that provides high performance and low jitter clock resources for selectiio logical resources

Bufgmux can be reused between two global clock resources. It can also be used as a normal bufg clock buffer. This buffer can only directly drive global clock cabling resources and only drive clock input; of course, the clock input of the FPGA internal logic trigger can also come from those common wiring resources, but those common wiring resources will have great clock jitter.

Bufpll and bufio2 are used to drive the clock resources of the I/O local clock network, which limits their purpose. They can only be used for the input clock resources of iserdes or oserdes resources;

Bufio2 can drive the iserdes2 and oserdes2 clock of SDR and DDR. bufio2 can route the input clock of gclk or gtp_dual tile to the clock input of bufg, DCM, and PLL. Bufio2_2clk can be used to replace the design clock of bufio2s used in iserdes2 and oserdes2 of DDR.

Similarly, the bufpll can drive the I/O clock network of the SDR clock. The bufpll connects the clkout0 or clkout1 of the PLL to the I/O local clock network.

By providing connections between logical resources and global clock cabling horizontal areas, bufh provides a richer array of Low-jitter clock resources.

1.1. Global clock Structure

 

Figure 1? 1. Global clock Structure

The global clock network of the Spartan-6 FPGA is driven by 16 bufgmux in the center of the device. The clock input can come from the top, bottom, left, and right bank of the FPGA, it can also be from the PLL or DCM; 16 bufgmux drives the vertical spine and transmits it to the North-South direction through the vertical spine. According to this line, the clock horizontally extends to the hclk clock column and provides the path to access the local logical primitive through the hclk clock column. Each hclk column has 16 horizontal clock buffers on both sides of the bufh driver to drive the Left and Right logical resources.

 

Figure 1? 2 bufh clock cabling path

On the Spartan-6 FPGA device, there are 32 gclk inputs, but there are only 16 global clock buffers. That is to say, each global clock buffer can only be driven by one of the two gclks, when both gclks (assuming gclk_a and gclk_ B share the bufgmx_c) are required, to provide more flexibility for users, gclk_a pins can be routed to bufgmux_c, while gclk_ B uses bufio2 to indirectly route to another bufgmux_d. However, a time delay may occur when the clock is cabled by bufio2.

Table 1? 1. Table of incomplete global clock resources shared by bank0 and bank1

 

 

Figure 1? Connection between 3bank0 and bank1 bufgmux

 

Figure 1? Connection between 4bank2 and bank3 bufgmux

For the design that uses the guid transceiver, each reference clock is associated with a bufio2, which may affect the use of Global clock pins on bank0 and bank2. For the SDR interface, what is the conflict between gclk Pin Input and? As shown in table 2, for the DDR interface, two bufio2 buckets are required for the GDR interface. Because the DDR interface needs to reverse the clock, the DDR interface conflicts with the gclk Pin Input, as shown in Table 1? 3.

Table 1? Input conflict of bufio2 in 2sdr Interface Usage

 

Table 1? Bufio2 input conflicts in the use of the 3ddr Interface

 

 

1.2. Io clock Structure

 

1? 5io clock Structure

All selection logic resources (input registers, output registers, iddr2, oddr2, iserdes2, and oserdes2) must be driven by the clock from the bufio2. Each bufio2 clock domain has four high-speed I clocks, it is driven by four dedicated bufio2 buffer; spartan6 FPGA has four bufio2 clock domains with a total of 32bufio2.

 

1? 6bufio2 Clock Domain

 

 

2. clock input

The clock input pin accepts external clock signals and connects them directly to the bufgmux or bufio2 primitive. Of course, the clock pin can also be used as a common Io. In addition to inputting the clock into the IO clock network, bufio2 also provides a dedicated clock route to the PLL/DCM or bufg.

 

2? 1 dedicated clock input cabled by bufio2

For the Spartan-6 FPGA, the dedicated clock input pin is located at the center of the chip edge. The clock pin layout of the 4-bank Spartan-6 FPGA is illustrated.

 

2? 2 four-bank Spartan-6 FPGA clock pin Layout

 

 

 

3. Clock management technology

The CMT (clock Management Unit) of the Spartan-6 FPGA provides a very flexible and high-performance clock. The CMT module of the Spartan-6 FPGA is located in the middle column of the vertical global Clock Tree, each CMT contains 2 DCM and 1 PLL.

 

3? 1spartan-6 fpga cmt Location Map

 

3? 2 CMT Structure Diagram

3.1. Functions of DCM

DCM: Digital Clock management, short for Digital Clock management unit. With advanced clock capabilities, DCM can directly import the clock into the global Clock Distribution Network. DCM can solve various clock problems, especially in the high performance and high frequency fields.

• Eliminates clock jitter and improves the performance of the entire system.
• Adjusts the phase of a clock signal.
• Frequency Doubling or frequency division of the input clock can also generate a new clock frequency by dynamically or statically providing the multiplication and division factor.
• To make the clock signal healthier, the duty cycle is stable at 50%
• Mirror, forward, and re-buffer a clock signal, deshake the input clock signal or convert it to a differential Io level.
• Clock input jitter Filtering
• Spread Spectrum Clock generation
• Oscillator operating mode

 

3? 3dcm Structure Diagram

3.2. Functions of PLL

PLL: Phase-Locked Loop. The Spartan-6 FPGA device contains six CMT tile. The main purpose of the PLL is to act as a jitter filter or frequency synthesizer for the external clock or internal clock.

 

3? 4pll Structure Diagram

 

Spartan6 series-spartan6 series-in-depth explanation of chip clock Resources