SPI bus SPI interface SPI protocol SPI mode SPI communication

SPI interface

SPI interface Introduction
SPI is a synchronous serial transmission specification released by Motorola. It is often used as a serial expansion interface for MCU peripheral chip. SPI has four pins: SS (from device Selection Line), SDO (serial data output line), SDI (serial data input line), and sck (synchronous serial clock line ). SPI can send and receive 8 (16) BIT data simultaneously in full duplex communication mode. The process is as follows: the host starts the sending process and sends the clock pulse signal, the data in the master shift register is migrated to the slave shift register through SDO, and the data in the shift register is moved to the master shift register through SDI. After 8 (16) clock pulses, the clock stops. All the 8 (16) data in the master shift register is moved to the slave shift register.
Auto load in the receiving buffer, the slave receives the buffer full flag (BF) and interrupt flag (sspif) set to "1 ". Similarly, all the eight-bit data in the shift register is transferred to the Master Register, and is automatically loaded to the master receiving buffer immediately. set the full flag (BF) and interrupt flag (sspif) of the master receiving buffer to "1 ". After the master CPU detects the full or interrupt mark position 1 of the master receiving buffer, it can read the data in the receiving buffer. Similarly, after the CPU detects that the receiving buffer is full or the interrupt flag is 1, the data in the receiving buffer can be read to complete the communication process. Here, dspic30f6014 is set as the master controller, and isd4002 is the slave device. The communication control process is completed through the SPI port.

SPI bus protocol

SPI is a ring bus structure consisting of SS (CS), sck, SDI, and SDO. Its timing is actually very simple, mainly under the control of sck, two two-way shift registers for data exchange.
Assume that the following 8-bit registers are installed with 10101010 of the data to be sent, and the rising edge sends, the falling edge receives, and the High Level sends the data first.
When the first rising edge comes, the data will be SDO = 1; register = 0101010x. When the descent edge arrives, the level on SDI will be stored in the register, then the register = 01010sdi, so that after 8 clock pulses, the content of the two registers is exchanged once. In this way, an SPI sequence is completed.
Example:
Assume that the host and slave are ready for initialization: And the sbuff of the host is 0xaa, And the sbuff of the slave is 0x55, next, we will demonstrate the eight clock cycles of SPI step by step: assume that the rising edge sends data

Pulse	Host sbuff	Slave sbuff	SDI	SDO
0	10101010	01010101	0	0
1 On	0101010x	1010101x	0	1
1 lower	01010100	10101011	0	1
2.	1010100x	0101011x	1	0
2	10101001	01010110	1	0
3.	0101001x	1010110x	0	1
3 lower	01010010	10101101	0	1
4.	1010010x	0101101x	1	0
4 lower	10100101	01011010	1	0
Top 5	0100101x	1011010x	0	1
Under 5	01001010	10110101	0	1
6 on	1001010x	0110101x	1	0
Under 6	10010101	01101010	1	0
On 7	0010101x	1101010x	0	1
Under 7	00101010	11010101	0	1
On 8	0101010x	1010101x	1	0
Under 8	01010101	10101010	1	0

This completes the 8-bit switching between two registers. The above indicates the rising edge, the lower indicates the falling edge, and SDI and SDO are relative to the host. When the SS pin is used as the host, the slave can select it as the slave and the slave can be used as the chip selection pin. According to the above analysis, a complete transmission cycle is 16 bits, that is, two bytes, because the host must first send commands and then prepare data from the host based on the host name, the Host reads data only in the next 8-bit clock cycle.

The SPI bus is a three-line synchronous interface launched by Motorola for Synchronous Serial Communication: A clock line sck, a data input line MoSi, and a data output line miso; it is used for full-duplex and synchronous serial communication between the CPU and various peripheral devices. SPI has the following features: it can send and receive serial data at the same time, work as a host or slave machine, provide a frequency programmable clock, send end interrupt sign, write conflict protection, and bus competition protection. Figure 3 shows the four modes in which the SPI bus works, among which the most widely used are the spi0 and SPI3 modes (expressed by solid line ):

Figure 2 four modes of SPI bus operation

SPI bus interface in a timely manner
In order to exchange data with peripherals, the SPI module can output serial synchronization clock polarity and phase according to the working requirements of peripherals. The clock polarity (cpol) has no significant impact on the transmission protocol. If cpol = 0, the idle status of the serial synchronization clock is low. If cpol = 1, the idle status of the serial synchronization clock is high. The Clock Phase (cpha) can be configured to select one of two different transmission protocols for data transmission. If cpha = 0, data in the first hop (up or down) of the serial synchronization clock is sampled; If cpha = 1, data in the second hop (up or down) of the serial synchronization clock is sampled. The SPI main module and the peripheral sound Clock Phase and polarity of the communication should be consistent. SPI bus interface timing.
 

Design of SPI function module

According to the function definition and the working principle of SPI, the entire IP core is divided into eight sub-modules: UC interface module, clock division module, data transmission FIFO module, data receiving FIFO module, state machine module, data sending logic module, data receiving logic module, and interrupt form module.

By in-depth analysis of the four SPI transmission protocols, we can find that the other three protocols can be obtained by converting the serial synchronous clock. To simplify the design, If You Want To transmit multiple data in a row, insert a serial clock to idle wait between two data transmissions so that the state machine only needs two States (idle and working) it will work correctly.