[state-Embedded notes] [036] [Close MMU and cache]

Close the MMU and cache

1.Cache is a small, but very fast-access memory that holds a copy of the data in the most recently used memory. By function divided into icache (instruction cache) and Dcache (data cache)

2. The virtual address is the address used in the program, and the physical address is the actual address used in the physical storage unit. Virtual addresses allow the process to use a larger amount of space. The role of the MMU is to complete the conversion of the virtual address to the physical address

3. During the processor initialization phase, to prevent unexpected errors, you need to temporarily close the MMU and cache

Both the 4.MMU and the cache are controlled by the CP15 Coprocessor's R1 (Control Register) M (0-bit), C (2), I (12-bit), and R7 invalidate i/d caches. The I bit can be ignored because downloading to NAND flash does not involve instruction caches. The manual in the arm core can be found in the relevant description

5. The first step invalidates the Icahce and Dcache, and the second closes the ICAHCE, Dcache and MMU.

/** Name: disable_cache_mmu* Description: Close cache and MMU*/DISABLE_CACHE_MMU:MCR P15, 0, R0, C7, C7, 0   //disable cache MRC P15, 0, R0, C1, C0, 0   //load C1 to R0BICR0, R0, #0x5   //Clear 0 (-c-m) MCR P15, 0, R0, C1, C0, 0   //save R0 to C1mov pc, LR

[state-Embedded notes] [036] [Close MMU and cache]