Step 2 of Self-writing processor (4) -- Circuit Design Example

I will upload my new book "self-writing processor" (not published yet). Today is the eighth article. I try to write this article every Thursday.

2.7 Circuit Design Example

In this section, we will design a simplified processor command acquisition circuit, through which we can use the example to understand the use of Tilde.

There is usually a PC register inside the processor, where the instruction address is stored. during normal operation, the PC value increases with time and the instruction of the corresponding address is retrieved from the instruction memory. Therefore, this section describes the processor command circuit, which consists of two parts: PC module and instruction memory.

1. Design and Implementation of the PC Module

The function of the PC module is to give the command address and increase the number of command addresses in each clock cycle. The interface design is shown in 2-13. Use the input interface on the left and the output interface on the Right To facilitate understanding. The interface function is described in Table 2-5.

The instruction address PC is defined as 6 in width. The main code of the PC module is as follows. For details, refer to the pc_reg.v file under the CD Code \ Chapter2 directory in this book.

Module pc_reg (inputwire CLK, input wire rst, output Reg [5:0] PC, output Reg CE); always @ (posedge CLK) begin // when the IF (RST = 1 'b1) begince <= 1' B0 is triggered on the rising edge of the clock signal; // when the reset signal is valid, the instruction memory enabling signal is invalid end else begince <= 1 'b1; // when the reset signal is invalid, the instruction memory enabling signal valid endalways @ (posedge CLK) begin // trigger if (Ce = 1 'b0) beginpc <= 6 'h00; // when the instruction memory enabling signal is invalid, when the PC remains 0 end else begin Pc <= PC + 1 'b1; // when the instruction memory enables effective signals, the PC adds 1 endendendmodule to each clock

2. Design and Implementation of instruction memory Rom

Instruction memory Rom is used to store instructions and give instructions for the corresponding address based on the input address. As shown in Figure 2-14, the left side is the input interface, and the right side is the output interface, which is easy to understand. The interface description is shown in Table 2-6.

The instruction width is defined as 32. The main code of the instruction memory Rom is as follows. For details, refer to the Rom. V file in the Code \ Chapter2 directory of this book.

Module Rom (input wire ce, input wire [5:0] ADDR, output Reg [31: 0] insT); Reg [31: 0] rom [63: 0]; // use a two-dimensional vector to define the memory always @ (*) begin if (Ce = 1 'b0) begininst <= 32' H0; // The enable signal is invalid, the given data is 0 end else begin inst <= Rom [ADDR]; // when the enabling signal is valid, the endendmodule of the command corresponding to the ADDR address is provided.

A two-dimensional vector memory is used to define the memory. The depth is 64, and the width of each element is 32, which is also the reason for using a 6-bit address.

3. Top-level files

First, we will introduce the knowledge of component instantiation. during the implementation of a complex circuit, we can divide it into multiple functional units for implementation, then, in a top-level file, call each function unit and connect it together in a certain way to realize the final circuit. The process of calling function units is called component examples. The component sample format is 2-15.

After the two steps above, we have implemented the PC module and instruction memory Rom respectively. Now we can write a top-level file to connect the two. The connection method is 2-16.

The output PC of the PC module is connected to the ADDR address interface of the instruction memory Rom, And the enable signal ce output by the PC module is connected to the enable signal interface CE of the RoM. The module corresponding to the top-level module is named inst_fetch and has three interfaces. The interface description is shown in Table 2-7.

The main code of the inst_fetch module is as follows: PC module and instruction memory Rom are used as examples. For more information, see the inst_fetch.v file in the "Code \ Chapter2" directory on the CD-ROM.

Module inst_fetch (inputwireclk, input wirerst, output wire [31: 0] inst_o); wire [] PC; wire rom_ce; // examples of PC module pc_reg pc_reg0 (. CLK (CLK ),. RST (RST ),. PC (PC ),. ce (rom_ce); // example Rom rom0 (. ce (rom_ce ),. ADDR (PC ),. inst (inst_o); endmodule

The output PC of the PC module and the input ADDR of the RoM module are connected to the variable PC, so the two are connected together. The output CE of the PC module and the input CE of the RoM module are connected to rom_ce, so the two are connected together. In this way, the connection relationship shown in Figure 2-16 is realized.

Next time, we will introduce how to simulate it. It is not complete!

Step 2 of Self-writing processor (4) -- Circuit Design Example