Step 5 of Self-writing CPU (2) -- openmips's solutions to data-related problems

I will upload my new book "Write CPU by myself" (not published yet). Today is 16th articles. I try to write them every Thursday.

5.2 openmips solutions to data-related problems

The openmips processor uses the data push method to solve the data-related issues in the pipeline. Add some signals to the original data flow diagram in Figure 4-4 to complete data push, as shown in Figure 5-7. It mainly pushes the results of the execution phase and the results of the memory access phase to the decoding phase and participates in the process of selecting the source operand in the decoding phase.

Figure 5-8 shows the changes made to the openmips system structure for data push. There are two aspects.

(1) The calculation results of the commands that will be in the pipeline stage, including: whether to write the destination register wreg_o, the destination Register address wd_o, and the data wdata_o to be written into the destination register to the decoding stage, as shown in the dotted line between 5 and 8.

(2) The operation results of commands that are in the pipeline access stage, including: whether to write the destination register wreg_o, the destination Register address wd_o, and the data wdata_o to be written into the destination register to the decoding stage.

For this reason, the ID module of the decoding stage should add interfaces as shown in Table 5-1.

The ID module in the decoding phase performs a comprehensive judgment based on the information sent to solve data problems and provides the operands to be involved in the calculation. The code of the ID module must be modified as follows. The main modification part is in bold or italic. The modified code is located in the ID. V file under the Code \ chapter5_1 directory on the CD-ROM of this book.

Module ID (...... // input wire ex_wreg_ I, input wire ['regbus] ex_wdata_ I, input wire ['regaddrbus] ex_wd_ I, // input wire mem_wreg_ I, input wire ['regbus] mem_wdata_ I, input wire ['regaddrbus] mem_wd_ I ,...... // The Source operand 1 sent to the execution stage, the source operand 2 output Reg ['regbus] reg1_o, output Reg ['regbus] reg2_o ,......);...... // The process of assigning values to reg1_o adds two situations: // 1. If the register to be read by the regfile module reading Port 1 is the target register to be written in the execution phase, // use the result ex_wdata_ I in the execution phase as the value of reg1_o. // 2. If the register to be read by the read Port 1 of the regfile module is the target register to be written in the memory access phase, // use mem_wdata_ I as the value of reg1_o directly; always @ (*) begin if (RST = 'rstenable) beginreg1_o <= 'zeroword; end else if (reg1_read_o = 1 'b1) & (ex_wreg_ I = 1 'b1) & (ex_wd_ I = reg1_addr_o) beginreg1_o <= ex_wdata_ I; end else if (reg1_read_o = 1 'b1) & (mem_wreg_ I = 1 'b1) & (mem_wd_ I = reg1_addr_o) beginreg1_o <= mem_wdata_ I; end else if (reg1_read_o = 1 'b1) Begin reg1_o <= reg1_data_ I; end else if (reg1_read_o = 1 'b0) Begin reg1_o <= Imm; end else begin regstmo <= 'zeroword; endend // adds two conditions for assigning values to reg2_o: // 1. If the register to be read by the read Port 2 of the regfile module is the destination register to be written in the execution phase, // the result of the execution phase ex_wdata_ I is directly used as the value of reg2_o; // 2. If the register to be read by the read Port 2 of the regfile module is the destination register to be written in the memory access phase, // The mem_wdata_ I result of the access phase is directly used as the value of reg2_o; always @ (*) begin if (RST = 'rstenable) beginreg2_o <= 'zeroword; end else if (reg2_read_o = 1 'b1) & (ex_wreg_ I = 1 'b1) & (ex_wd_ I = reg2_addr_o) beginreg2_o <= ex_wdata_ I; end else if (reg2_read_o = 1 'b1) & (mem_wreg_ I = 1 'b1) & (mem_wd_ I = reg2_addr_o) beginreg2_o <= mem_wdata_ I; end else if (reg2_read_o = 1 'b1) begin reg2_o <= reg2_data_ I; end else if (reg2_read_o = 1 'b0) Begin reg2_o <= Imm; end else begin reg2_o <= 'zeroword; endendendendmodule

In addition to modifying the code of the ID module of the decoding stage, you also need to modify the code corresponding to the top-level module openmips and add the connection relationship shown in Figure 5-8. The specific modification process is not listed in the document. You can refer to the openmips. V file under the Code \ chapter5_1 directory attached to the book. (The Code will be uploaded later)

5.3 test data-related problem solving results

The test procedure is as follows. There are three raw-related cases discussed in section 5.1. The source file is the inst_rom.s file under the CD Code \ chapter5_1 \ asmtest directory.

.org 0x0.global _start.set noat_start:   ori $1,$0,0x1100        # $1 = $0 | 0x1100 = 0x1100   ori $1,$1,0x0020        # $1 = $1 | 0x0020 = 0x1120   ori $1,$1,0x4400        # $1 = $1 | 0x4400 = 0x5520   ori $1,$1,0x0044        # $1 = $1 | 0x0044 = 0x5564

The command comments provide the expected execution results. Copy the inst_rom.s file to bin2mem.exe, makefile, and ram. the three LD files are copied to the same directory in the Ubuntu Virtual Machine. Open the terminal, run the CD command to enter the directory, and then enter make all to obtain the inst_rom.data file that can be used for Modelsim simulation.

Create a new project in Modelsim, add all. V files under the CD Code \ chapter5_1 directory attached to this book, and compile the project. Copy the above inst_rom.data file to the directory of The Modelsim project to perform simulation. For detailed steps for creating a project and simulation in Modelsim, see Chapter 2nd.

Run the simulation and observe the changes in the register $1 value, as shown in Figure 5-9. The change in $1 is as expected. Therefore, the modified openmips solves the data-related problems correctly.

The next step will implement logic, shift, and empty commands. Stay tuned!