Step 8 of Self-writing CPU (2) -- Transfer Instruction implementation

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8.3 Transfer Instruction Implementation ideas 8.3.1 Implementation ideas

According to the discussion in section 8.1, in order to minimize the loss caused by the transfer instruction, openmips judges the transfer condition in the decoding phase. If the transfer condition is met, modify the PC as the transfer target address.

8.3.2 modify a data flow chart

To implement the transfer instruction, modify the data flow as shown in Figure 8-5.

 

It can be seen that there are multiple transfer judgment steps in the decoding phase. In addition, the PC value can be changed to three cases.

Scenario 1: PC + 4. This is generally the case where each time period of PC plus 4 points to the next instruction.

Case 2: The PC remains unchanged. This happens when the pipeline is suspended. See the implementation of the pipeline suspension in Chapter 1.

Case 3: PC is equal to the transfer judgment result. If the transfer instruction meets the transfer condition, the transfer destination address is assigned to the PC.

8.3.3 System Structure Modification

To implement the transfer instruction, you need to modify the system structure and add some module interfaces, as shown in Figure 8-6.

The following are some notes.

(1) If the instruction in the decoding stage is a transfer instruction and the transfer condition is met, the ID module sets branch_flag_o as branch, and provides the transfer destination address through the branch_target_address_o interface, sent to the PC module, and the latter modifies the access address accordingly.

(2) If the instruction in the decoding stage is a transfer instruction and the transfer condition is met, the ID module also sets next_inst_in_delayslot_o to indelayslot, indicating that the next instruction is a delay slot instruction, indelayslot is a macro definition. The next_inst_in_delayslot_o signal is sent to the ID/ex module and sent back to the ID module through the is_in_delayslot_o interface of the ID/ex module in the next clock cycle, the ID module can determine whether the instruction in the decoding stage is a delay slot instruction.

(3) If the Transfer Instruction needs to save the return address, the ID module also needs to calculate the return address and output it through the link_addr_o interface. The value is finally transmitted to the ex module, the value of the destination register to be written.

Next, modify the code to implement the transfer instruction.

 

 

Step 8 of Self-writing CPU (2) -- Transfer Instruction implementation