void Rcc_deinit (void)
{
RCC->CR |= (uint32_t) 0x00000001; Turn on the internal 8MHz clock
#ifndef STM32F10X_CL//stm32f10x_cl refers to the STM32 Interconnect series microprocessor
Rcc->cfgr &= (uint32_t) 0xf8ff0000; 27-31 bits in the CFGR register of other types of processors are reserved bits and 24-26 are MCO bits
#else//And the CFGR register of the interconnected processor, 28-31 bits are reserved bits and 24-27 are MCO
Rcc->cfgr &= (uint32_t) 0xf0ff0000; Initialize the CFGR register, see note 1th
#endif
RCC->CR &= (uint32_t) 0xfef6ffff; Initialize the CR register, see note 2nd
RCC->CR &= (uint32_t) 0xFFFBFFFF; Bit 18=0,hse is not bypassed and can only be set when HSE is closed
Rcc->cfgr &= (uint32_t) 0xff80ffff; Set CFGR Register, see note 3rd
#ifdef STM32F10X_CL//Interconnect microcontroller settings
RCC->CR &= (uint32_t) 0xEBFFFFFF;
Rcc->cir = 0x00ff0000;
RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) | | Defined (STM32F10X_MD_VL) | | Defined (STM32F10X_HD_VL)
Rcc->cir = 0x009f0000; Initialize the CIR clock interrupt register, see note 4th
RCC->CFGR2 = 0x00000000;
#else
Rcc->cir = 0x009f0000;
#endif
}
Comments:
1, Bit 26 (27) -24=000: The microcontroller does not have a clock output;
Bit 15-14=00:PCLK2 (APB2 clock) is used as the ADC clock after two divided;
Bit 13-11=000:HCLK does not divide, namely APB2 high-speed clock PCLK2 equals AHB clock;
Bit 10-8=000: Low speed APB1 clock (PCLK1) does not divide;
Bit 7-4=0000:AHB clock does not divide, equals the system clock SYSCLK;
Bit 3-2=00:HSI (internal high-speed clock) as the system clock;
Bit 1-0=00:HSI (internal high-speed clock) as the system clock.
2, bit 24=0:PLL closed;
Bit 19=0: The clock detector is off when the external clock is ready to open;
Bit 16=0: external clock HSE closed.
3, bit 22=0:PLL clock 1.5 times times the frequency as the USB clock;
Bit 21-18=0000:PLL twice multiplier output, only can be set when the PLL is off;
Bit 17=0:hse does not divide, only can be set when the PLL is closed;
The bit 16=0:hsi clock is 2-divided as the PLL input clock and can only be set when the PLL is turned off;
4, bit 23=1: Clear the clock security system interrupt flag bit;
Bit 20=1: Clears the PLL ready interrupt flag bit;
Bit 19=1: Clear the HSE ready interrupt sign bit;
Bit 18=1: Clear HSI Ready interrupt flag bit;
Bit 17=1: CLEAR the LSE-ready interrupt sign;
Bit 16=1: Clears LSI ready interrupt flag bit.
STM32 Clock library function Rcc_deinit Introduction
